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    • 2. 发明授权
    • Method and apparatus for providing higher order modulation that is backwards compatible with quaternary phase shift keying(QPSK) or offset quaternary phase shift keying (OQPSK)
    • 用于提供与四相相移键控(QPSK)或偏移四相相移键控(OQPSK)向后兼容的更高阶调制的方法和装置,
    • US08199847B2
    • 2012-06-12
    • US11879607
    • 2007-07-18
    • Lin-Nan LeeFeng-Wen SunMustafa ErozYimin Jiang
    • Lin-Nan LeeFeng-Wen SunMustafa ErozYimin Jiang
    • H03C5/00H03D5/00H03K7/10H03K9/10
    • H04L27/3488H04L27/183
    • A method and apparatus for providing an asymmetrical backwards compatible communications signal that is capable of being decoded by QPSK and OQPSK receivers as well as PSK and QAM receivers is provided. The invention comprises a timing error accumulator coupled to a first bit stream. The first bit stream includes content that is common to the QPSK/OQPSK receiver and to the PSK/QAM receiver. A phase error accumulator is coupled to a second bit stream and adjusts the phase of symbols in the second bit stream. A phase and timing error compensator is coupled to the phase error accumulator and the timing error accumulator and adjusts the first and second bit streams received from the phase error accumulator and the timing error accumulator in order to reduce timing and phase errors. A higher order modulator coupled to the phase- and timing error compensator is also provided. The higher order modulator processes the first and second bit streams to provide the asymmetrical backwards compatible signal.
    • 提供一种提供能够被QPSK和OQPSK接收机以及PSK和QAM接收机解码的不对称向后兼容通信信号的方法和装置。 本发明包括耦合到第一位流的定时误差累加器。 第一比特流包括对于QPSK / OQPSK接收机和PSK / QAM接收机是共同的内容。 相位误差累加器被耦合到第二比特流并且调整第二比特流中的符号的相位。 相位和定时误差补偿器耦合到相位误差累加器和定时误差累加器,并调整从相位误差累加器和定时误差累加器接收的第一和第二比特流,以减少定时和相位误差。 还提供耦合到相位和定时误差补偿器的较高阶调制器。 高阶调制器处理第一和第二比特流以提供不对称的向后兼容信号。
    • 8. 发明申请
    • CODE DESIGN AND IMPLEMENTATION IMPROVEMENTS FOR LOW DENSITY PARITY CHECK CODES FOR MULTIPLE-INPUT MULTIPLE-OUTPUT CHANNELS
    • 用于多输入多输出通道的低密度奇偶校验码的代码设计和实现改进
    • US20100192038A1
    • 2010-07-29
    • US12753528
    • 2010-04-02
    • Mustafa ErozLin-Nan LeeFeng-Wen Sun
    • Mustafa ErozLin-Nan LeeFeng-Wen Sun
    • H03M13/05G06F11/10
    • H03M13/1185H03M13/1137H03M13/152H03M13/2906H04B7/02H04L1/005H04L1/0057H04L1/0625
    • Methods and systems for designing LDPC codes are disclosed. A method in accordance with the present invention comprises configuring a plurality of parallel accumulation engines, a number of the plurality of parallel accumulation engines equal to M, accumulating a first information bit at a first set of specific parity bit addresses using the plurality of parallel accumulation engines, increasing a parity bit address for each member of the first set of specific parity bit addresses by a pre-determined offset for each new information bit, accumulating subsequent information bits at parity bit addresses that are offset from the specific parity bit addresses by a pre-determined offset until an M+1 information bit is reached, accumulating the next M information bits at a second set of specific parity bit addresses using the plurality of parallel accumulation engines, increasing a parity bit address for each member of the second set of specific parity bit addresses by the pre-determined offset for each new information bit; and repeating accumulating and increasing the addresses until the information bits are exhausted.
    • 公开了用于设计LDPC码的方法和系统。 根据本发明的方法包括配置多个并行累积引擎,多个并行累加引擎中的多个等于M,使用多个并行累加累积第一组特定奇偶校验位地址处的第一信息位 引擎,通过针对每个新信息位的预定偏移增加第一组特定奇偶校验位地址的每个成员的奇偶校验位地址,在与特定奇偶校验位地址偏移的奇偶校验位地址处累积后续信息比特 预定的偏移量直到达到M + 1信息位,使用多个并行累积引擎在第二组特定奇偶校验位地址累积下一个M个信息位,增加第二组的每个成员的奇偶校验位地址 特定奇偶校验位地址由每个新信息位的预定偏移量; 并重复累积和增加地址直到信息位耗尽。