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1. 发明申请

US20070263751A1 Method and apparatus for providing higher order modulation that is backwards compatible with quaternary phase shift keying(QPSK) or offset quaternary phase shift keying (OQPSK) 有权
标题翻译：用于提供与四相相移键控（QPSK）或偏移四相相移键控（OQPSK）向后兼容的更高阶调制的方法和装置，
公开(公告)号：US20070263751A1
公开(公告)日：2007-11-15
申请号：US11879607
申请日：2007-07-18
申请人： Lin-Nan Lee , Feng-Wen Sun , Mustafa Eroz , Yimin Jiang
发明人： Lin-Nan Lee , Feng-Wen Sun , Mustafa Eroz , Yimin Jiang
IPC分类号： H03D3/22
CPC分类号： H04L27/3488 , H04L27/183
摘要： A method and apparatus for providing an asymmetrical backwards compatible communications signal that is capable of being decoded by QPSK and OQPSK receivers as well as PSK and QAM receivers is provided. The invention comprises a timing error accumulator coupled to a first bit stream. The first bit stream includes content that is common to the QPSK/OQPSK receiver and to the PSK/QAM receiver. A phase error accumulator is coupled to a second bit stream and adjusts the phase of symbols in the second bit stream. A phase and timing error compensator is coupled to the phase error accumulator and the timing error accumulator and adjusts the first and second bit streams received from the phase error accumulator and the timing error accumulator in order to reduce timing and phase errors. A higher order modulator coupled to the phase- and timing error compensator is also provided. The higher order modulator processes the first and second bit streams to provide the asymmetrical backwards compatible signal.
摘要翻译：提供一种提供能够被QPSK和OQPSK接收机以及PSK和QAM接收机解码的不对称向后兼容通信信号的方法和装置。本发明包括耦合到第一位流的定时误差累加器。第一比特流包括对于QPSK / OQPSK接收机和PSK / QAM接收机是共同的内容。相位误差累加器被耦合到第二比特流并且调整第二比特流中的符号的相位。相位和定时误差补偿器耦合到相位误差累加器和定时误差累加器，并调整从相位误差累加器和定时误差累加器接收的第一和第二比特流，以减少定时和相位误差。还提供耦合到相位和定时误差补偿器的高阶调制器。高阶调制器处理第一和第二比特流以提供不对称的向后兼容信号。

2. 发明授权

US08199847B2 Method and apparatus for providing higher order modulation that is backwards compatible with quaternary phase shift keying(QPSK) or offset quaternary phase shift keying (OQPSK) 有权
标题翻译：用于提供与四相相移键控（QPSK）或偏移四相相移键控（OQPSK）向后兼容的更高阶调制的方法和装置，
公开(公告)号：US08199847B2
公开(公告)日：2012-06-12
申请号：US11879607
申请日：2007-07-18
申请人： Lin-Nan Lee , Feng-Wen Sun , Mustafa Eroz , Yimin Jiang
发明人： Lin-Nan Lee , Feng-Wen Sun , Mustafa Eroz , Yimin Jiang
IPC分类号： H03C5/00 , H03D5/00 , H03K7/10 , H03K9/10
CPC分类号： H04L27/3488 , H04L27/183
摘要： A method and apparatus for providing an asymmetrical backwards compatible communications signal that is capable of being decoded by QPSK and OQPSK receivers as well as PSK and QAM receivers is provided. The invention comprises a timing error accumulator coupled to a first bit stream. The first bit stream includes content that is common to the QPSK/OQPSK receiver and to the PSK/QAM receiver. A phase error accumulator is coupled to a second bit stream and adjusts the phase of symbols in the second bit stream. A phase and timing error compensator is coupled to the phase error accumulator and the timing error accumulator and adjusts the first and second bit streams received from the phase error accumulator and the timing error accumulator in order to reduce timing and phase errors. A higher order modulator coupled to the phase- and timing error compensator is also provided. The higher order modulator processes the first and second bit streams to provide the asymmetrical backwards compatible signal.
摘要翻译：提供一种提供能够被QPSK和OQPSK接收机以及PSK和QAM接收机解码的不对称向后兼容通信信号的方法和装置。本发明包括耦合到第一位流的定时误差累加器。第一比特流包括对于QPSK / OQPSK接收机和PSK / QAM接收机是共同的内容。相位误差累加器被耦合到第二比特流并且调整第二比特流中的符号的相位。相位和定时误差补偿器耦合到相位误差累加器和定时误差累加器，并调整从相位误差累加器和定时误差累加器接收的第一和第二比特流，以减少定时和相位误差。还提供耦合到相位和定时误差补偿器的较高阶调制器。高阶调制器处理第一和第二比特流以提供不对称的向后兼容信号。

3. 发明授权

US07260159B2 Method and apparatus for providing higher order modulation that is backwards compatible with quaternary phase shift keying (QPSK) or offset quaternary phase shift keying (OQPSK) 有权
标题翻译：用于提供与四相相移键控（QPSK）或偏移四相相移键控（OQPSK）向后兼容的更高阶调制的方法和装置，
公开(公告)号：US07260159B2
公开(公告)日：2007-08-21
申请号：US10142703
申请日：2002-05-10
申请人： Lin-Nan Lee , Feng-Wen Sun , Mustafa Eroz , Yimin Jiang
发明人： Lin-Nan Lee , Feng-Wen Sun , Mustafa Eroz , Yimin Jiang
IPC分类号： H03D3/22 , H04L27/22
CPC分类号： H04L27/3488 , H04L27/183
摘要： A method and apparatus for providing an asymmetrical backwards compatible communications signal that is capable of being decoded by QPSK and OQPSK receivers as well as PSK and QAM receivers is provided. The invention comprises a timing error accumulator coupled to a first bit stream. The first bit stream includes content that is common to the QPSK/OQPSK receiver and to the PSK/QAM receiver. A phase error accumulator is coupled to a second bit stream and adjusts the phase of symbols in the second bit stream. A phase and timing error compensator is coupled to the phase error accumulator and the timing error accumulator and adjusts the first and second bit streams received from the phase error accumulator and the timing error accumulator in order to reduce timing and phase errors. A higher order modulator coupled to the phase and timing error compensator is also provided. The higher order modulator processes the first and second bit streams to provide the asymmetrical backwards compatible signal.
摘要翻译：提供一种提供能够被QPSK和OQPSK接收机以及PSK和QAM接收机解码的不对称向后兼容通信信号的方法和装置。本发明包括耦合到第一位流的定时误差累加器。第一比特流包括对于QPSK / OQPSK接收机和PSK / QAM接收机是共同的内容。相位误差累加器被耦合到第二比特流并且调整第二比特流中的符号的相位。相位和定时误差补偿器耦合到相位误差累加器和定时误差累加器，并调整从相位误差累加器和定时误差累加器接收的第一和第二比特流，以减少定时和相位误差。还提供耦合到相位和定时误差补偿器的高阶调制器。高阶调制器处理第一和第二比特流以提供不对称的向后兼容信号。

4. 发明授权

US08392793B2 Code design and implementation improvements for low density parity check codes for multiple-input multiple-output channels 有权
标题翻译：用于多输入多输出通道的低密度奇偶校验码的代码设计和实现改进
公开(公告)号：US08392793B2
公开(公告)日：2013-03-05
申请号：US12753528
申请日：2010-04-02
申请人： Mustafa Eroz , Lin-Nan Lee , Feng-Wen Sun
发明人： Mustafa Eroz , Lin-Nan Lee , Feng-Wen Sun
IPC分类号： H03M13/00
CPC分类号： H03M13/1185 , H03M13/1137 , H03M13/152 , H03M13/2906 , H04B7/02 , H04L1/005 , H04L1/0057 , H04L1/0625
摘要： Methods include configuring M parallel accumulation engines, accumulating a first information bit at a first set of specific parity bit addresses using the accumulation engines, increasing a parity bit address for each member of the first set of specific parity bit addresses by a pre-determined offset for each new information bit, accumulating subsequent information bits at parity bit addresses that are offset from the specific parity bit addresses by a pre-determined offset until an M+1 information bit is reached, accumulating the next M information bits at a second set of specific parity bit addresses using the accumulation engines, increasing a parity bit address for each member of the second set of specific parity bit addresses by the pre-determined offset for each new information bit; and repeating accumulating and increasing the addresses until the information bits are exhausted. Related systems are described.
摘要翻译：方法包括配置M并行累积引擎，使用累积引擎在第一组特定奇偶校验位地址处累积第一信息位，将第一组特定奇偶校验位地址的每个成员的奇偶校验位地址增加预定的偏移量对于每个新的信息位，在与特定奇偶校验位地址相偏移的奇偶校验位地址处累积后续信息比特，直到达到M + 1个信息比特为止，将下一个M个信息比特累加在第二组使用累积引擎的特定奇偶校验位地址，增加第二组特定奇偶校验位地址的每个成员的奇偶校验位地址每个新信息比特的预定偏移量; 并重复累积和增加地址直到信息位耗尽。描述相关系统。

5. 发明申请

US20120221915A1 SATELLITE COMMUNICATION SYSTEM UTILIZING LOW DENSITY PARITY CHECK CODES 有权
标题翻译：卫星通信系统利用低密度奇偶校验码
公开(公告)号：US20120221915A1
公开(公告)日：2012-08-30
申请号：US13408953
申请日：2012-02-29
申请人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee , Dan Fraley
发明人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee , Dan Fraley
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1137 , H03M13/1165 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/255 , H03M13/2906 , H03M13/356 , H03M13/6505 , H04L1/005 , H04L1/0057 , H04L1/007
摘要： An approach for reliably communicating over a satellite in support of a communication service including, for example, as direct broadcast satellite and data service, is disclosed. An input message is encoded, yielding a structured Low Density Parity Check (LDPC) coded message. The coded message is modulated according to a high order modulation scheme that has a signal constellation representing more than two symbols per signaling point—e.g., 8-PSK (Phase Shift Keying) and 16-QAM (Quadrature Amplitude Modulation). The system includes a transmitter configured to propagate the modulated signal over the satellite. The above approach is particularly applicable to bandwidth constrained communication systems requiring high data rates.
摘要翻译：公开了一种用于通过卫星可靠地通信以支持包括例如直接广播卫星和数据服务在内的通信服务的方法。编码输入消息，产生结构化的低密度奇偶校验（LDPC）编码消息。编码消息根据高阶调制方案进行调制，该高阶调制方案具有每个信令点（例如8-PSK（相移键控）和16-QAM（正交幅度调制））多于两个符号的信号星座。该系统包括被配置成通过卫星传播调制信号的发射机。上述方法特别适用于需要高数据速率的带宽受限通信系统。

6. 发明授权

US08181085B2 Method and system for providing short block length low density parity check (LDPC) codes in support of broadband satellite applications 有权
标题翻译：提供支持宽带卫星应用的短块长度低密度奇偶校验（LDPC）码的方法和系统
公开(公告)号：US08181085B2
公开(公告)日：2012-05-15
申请号：US12943613
申请日：2010-11-10
申请人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
发明人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
IPC分类号： H03M13/00
CPC分类号： H03M13/255 , H03M13/1134 , H03M13/1165 , H03M13/118 , H03M13/152 , H03M13/2906
摘要： An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is imposed on the LDPC codes by restricting portion part of the parity check matrix to be lower triangular and/or satisfying other requirements such that the communication between bit nodes and check nodes of the decoder is simplified. Further, a cyclic redundancy check (CRC) encoder is supplied to encode the input signal according to a CRC code. This approach has particular application in digital video broadcast services over satellite.
摘要翻译：提供了一种用于编码短帧长度低密度奇偶校验（LDPC）码的方法。编码器生成具有外部Bose Chaudhuri Hocquenghem（BCH）码的LDPC码。通过将奇偶校验矩阵的部分部分限制为三角形和/或满足其他要求，使得解码器的位节点和校验节点之间的通信被简化，对LDPC码施加结构。此外，循环冗余校验（CRC）编码器被提供以根据CRC码对输入信号进行编码。这种方法在卫星数字视频广播业务中具有特殊应用。

7. 发明授权

US08028224B2 Method and system for providing short block length low density parity check (LDPC) codes 有权
标题翻译：提供短块长度低密度奇偶校验（LDPC）码的方法和系统
公开(公告)号：US08028224B2
公开(公告)日：2011-09-27
申请号：US12706686
申请日：2010-02-16
申请人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
发明人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
IPC分类号： G06F11/00
CPC分类号： H04L1/0065 , H03M13/1137 , H03M13/116 , H03M13/118 , H03M13/152 , H03M13/255 , H03M13/2906 , H04L1/0057 , H04L1/0071
摘要： An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a short LDPC code by shortening longer mother codes. The short LDPC code has an outer Bose Chaudhuri Hocquenghem (BCH) code. According to another aspect, for an LDPC code with code rate of ⅗ utilizing 8-PSK (Phase Shift Keying) modulation, an interleaver provides for interleaving bits of the output LDPC code by serially writing data associated with the LDPC code column-wise into a table and reading the data row-wise from right to left. The above approach has particular application in digital video broadcast services over satellite.
摘要翻译：提供了一种用于生成低密度奇偶校验（LDPC）码的方法。 LDPC编码器通过缩短较长的母码产生短的LDPC码。短LDPC码具有外部Bose Chaudhuri Hocquenghem（BCH）码。根据另一方面，对于利用8-PSK（相移键控）调制的码率为an的LDPC码，交织器通过串行地将与LDPC码相关联的数据串行地写入到从右到左逐行阅读数据。上述方法在卫星数字视频广播业务中具有特殊应用。

8. 发明申请

US20110060958A1 METHOD AND SYSTEM FOR PROVIDING SHORT BLOCK LENGTH LOW DENSITY PARITY CHECK (LDPC) CODES IN SUPPORT OF BROADBAND SATELLITE APPLICATIONS 有权
标题翻译：用于在宽带卫星应用支持下提供短块长度低密度奇偶校验（LDPC）码的方法和系统
公开(公告)号：US20110060958A1
公开(公告)日：2011-03-10
申请号：US12943613
申请日：2010-11-10
申请人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
发明人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/255 , H03M13/1134 , H03M13/1165 , H03M13/118 , H03M13/152 , H03M13/2906
摘要： An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is imposed on the LDPC codes by restricting portion part of the parity check matrix to be lower triangular and/or satisfying other requirements such that the communication between bit nodes and check nodes of the decoder is simplified. Further, a cyclic redundancy check (CRC) encoder is supplied to encode the input signal according to a CRC code. This approach has particular application in digital video broadcast services over satellite.
摘要翻译：提供了一种用于编码短帧长度低密度奇偶校验（LDPC）码的方法。编码器生成具有外部Bose Chaudhuri Hocquenghem（BCH）码的LDPC码。通过将奇偶校验矩阵的部分部分限制为三角形和/或满足其他要求，使得解码器的位节点和校验节点之间的通信被简化，对LDPC码施加结构。此外，循环冗余校验（CRC）编码器被提供以根据CRC码对输入信号进行编码。这种方法在卫星数字视频广播业务中具有特殊应用。

9. 发明授权

US07856586B2 Method and system for providing short block length low density parity check (LDPC) codes in support of broadband satellite applications 有权
标题翻译：提供支持宽带卫星应用的短块长度低密度奇偶校验（LDPC）码的方法和系统
公开(公告)号：US07856586B2
公开(公告)日：2010-12-21
申请号：US12252216
申请日：2008-10-15
申请人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
发明人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
IPC分类号： H03M13/00
CPC分类号： H03M13/255 , H03M13/1134 , H03M13/1165 , H03M13/118 , H03M13/152 , H03M13/2906
摘要： An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is imposed on the LDPC codes by restricting portion part of the parity check matrix to be lower triangular and/or satisfying other requirements such that the communication between bit nodes and check nodes of the decoder is simplified. Further, a cyclic redundancy check (CRC) encoder is supplied to encode the input signal according to a CRC code. This approach has particular application in digital video broadcast services over satellite.
摘要翻译：提供了一种用于编码短帧长度低密度奇偶校验（LDPC）码的方法。编码器生成具有外部Bose Chaudhuri Hocquenghem（BCH）码的LDPC码。通过将奇偶校验矩阵的部分部分限制为三角形和/或满足其他要求，使得解码器的位节点和校验节点之间的通信被简化，对LDPC码施加结构。此外，循环冗余校验（CRC）编码器被提供以根据CRC码对输入信号进行编码。这种方法在卫星数字视频广播业务中具有特殊应用。

10. 发明申请

US20100107032A1 BIT LABELING FOR AMPLITUDE PHASE SHIFT CONSTELLATION USED WITH LOW DENSITY PARITY CHECK (LDPC) CODES 有权
标题翻译：用于具有低密度奇偶校验（LDPC）编码的AMPLITUDE相位移位协议的比特标签
公开(公告)号：US20100107032A1
公开(公告)日：2010-04-29
申请号：US12498968
申请日：2009-07-07
申请人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
发明人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
IPC分类号： H03M13/13 , G06F11/10
CPC分类号： H03M13/13 , H03M13/1137 , H03M13/1165 , H03M13/1515 , H03M13/152 , H03M13/255 , H03M13/2906 , H03M13/2927 , H03M13/6306 , H04L1/0041 , H04L1/0057 , H04L1/0071 , H04L27/186 , H04L27/2053
摘要： An approach is provided for bit labeling of a signal constellation. A transmitter generates encoded signals using, according to one embodiment, a structured parity check matrix of a Low Density Parity Check (LDPC) code. The transmitter includes an encoder for transforming an input message into a codeword represented by a plurality of set of bits. The transmitter includes logic for mapping non-sequentially (e.g., interleaving) one set of bits into a higher order constellation (Quadrature Phase Shift Keying (QPSK), 8-PSK, 16-APSK (Amplitude Phase Shift Keying), 32-APSK, etc.), wherein a symbol of the higher order constellation corresponding to the one set of bits is output based on the mapping.
摘要翻译：提供了一种用于信号星座的位标记的方法。根据一个实施例，发射机使用低密度奇偶校验（LDPC）码的结构奇偶校验矩阵来生成编码信号。发射机包括用于将输入消息变换成由多个位组表示的码字的编码器。发射机包括用于将一组比特的非顺序（例如，交织）映射成更高阶的星座（正交相移键控（QPSK），8-PSK，16-APSK（振幅相移键控），32-APSK，等等），其中基于该映射输出对应于该一组比特的较高阶星座的符号。

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