专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08484448B2 Information processing device 有权
标题翻译：信息处理装置
公开(公告)号：US08484448B2
公开(公告)日：2013-07-09
申请号：US13399023
申请日：2012-02-17
申请人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
发明人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
IPC分类号： G06F9/00 , G06F15/177
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： Information processing system including a first and a second operation mode with operating current lower than the first, a register holding an address of an instruction executed by a processing unit first when a boot address register returns from second to first operation mode, wherein the address is output to the processing unit when second to first operation mode shifting, wherein the boot address register is rewritable, an information holding circuit holding a value of a peripheral circuit module register, wherein the information holding circuit holds, in the second operation mode, information about the peripheral circuit module register, and, transfers information held in the information holding circuit to the peripheral circuit module register regarding a second-to-first operation mode shift, and wherein when an interrupt request is posted from outside the system in the second operation mode, the information processing system performs interrupt processing corresponding to the interrupt request.
摘要翻译：信息处理系统，包括具有低于第一操作电流的第一操作模式和第二操作模式，当引导地址寄存器从第二操作模式返回到第一操作模式时，首先保存由处理单元执行的指令的地址的寄存器，其中该地址为当第二至第一操作模式转换时，输出到处理单元，其中引导地址寄存器是可重写的，信息保持电路保持外围电路模块寄存器的值，其中信息保持电路在第二操作模式中保持关于外围电路模块寄存器，并且将关于第二至第一操作模式移位的信息保持电路中保存的信息传送到外围电路模块寄存器，并且其中当在第二操作模式中从系统外部发布中断请求时信息处理系统执行与内部相对应的中断处理破产请求

2. 发明申请

US20120151197A1 INFORMATION PROCESSING DEVICE 有权
标题翻译：信息处理设备
公开(公告)号：US20120151197A1
公开(公告)日：2012-06-14
申请号：US13399023
申请日：2012-02-17
申请人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
发明人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
IPC分类号： G06F9/00
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： Information processing system including a first and a second operation mode with operating current lower than the first, a register holding an address of an instruction executed by a processing unit first when a boot address register returns from second to first operation mode, wherein the address is output to the processing unit when second to first operation mode shifting, wherein the boot address register is rewritable, an information holding circuit holding a value of a peripheral circuit module register, wherein the information holding circuit holds, in the second operation mode, information about the peripheral circuit module register, and, transfers information held in the information holding circuit to the peripheral circuit module register regarding a second-to-first operation mode shift, and wherein when an interrupt request is posted from outside the system in the second operation mode, the information processing system performs interrupt processing corresponding to the interrupt request.
摘要翻译：信息处理系统，包括具有低于第一操作电流的第一操作模式和第二操作模式，当引导地址寄存器从第二操作模式返回到第一操作模式时，首先保存由处理单元执行的指令的地址的寄存器，其中该地址为当第二至第一操作模式转换时，输出到处理单元，其中引导地址寄存器是可重写的，信息保持电路保持外围电路模块寄存器的值，其中信息保持电路在第二操作模式中保持关于外围电路模块寄存器，并且将关于第二至第一操作模式移位的信息保持电路中保存的信息传送到外围电路模块寄存器，并且其中当在第二操作模式中从系统外部发布中断请求时信息处理系统执行与内部相对应的中断处理破产请求

3. 发明授权

US08122233B2 Information processing device 有权
标题翻译：信息处理装置
公开(公告)号：US08122233B2
公开(公告)日：2012-02-21
申请号：US12124232
申请日：2008-05-21
申请人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
发明人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
IPC分类号： G06F9/00 , G06F15/177
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： An information processing device, including: a processing unit; a peripheral circuit module; and a boot address register, wherein the information processing device comprises a first operation mode and a second operation mode having an operating current which is lower than that of said first operation mode, wherein the boot address register holds an address of an instruction to be executed by said processing unit first when the boot address register returns from said second operation mode to said first operation mode, wherein the address is output from said boot address to the processing unit when said information processing device shifts from said second operation mode to said first operation mode.
摘要翻译：一种信息处理装置，包括：处理单元; 外围电路模块; 以及引导地址寄存器，其中所述信息处理设备包括具有低于所述第一操作模式的操作电流的第一操作模式和第二操作模式，其中所述引导地址寄存器保存要执行的指令的地址所述处理单元首先当所述引导地址寄存器从所述第二操作模式返回到所述第一操作模式时，其中当所述信息处理设备从所述第二操作模式转换到所述第一操作时，所述地址从所述引导地址输出到所述处理单元模式。

4. 发明授权

US07380149B2 Information processing device 有权
标题翻译：信息处理装置
公开(公告)号：US07380149B2
公开(公告)日：2008-05-27
申请号：US10849063
申请日：2004-05-20
申请人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
发明人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
IPC分类号： G06F1/26 , G06F1/24 , G06F1/32 , G06F1/04
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： A mechanism of making a low standby current caused by power off compatible with a fast return operation from a standby caused by an interrupt is realized. An information processing device has a first area that includes a central processing unit and peripheral circuit modules, a second area having information holding circuits for holding values of registers contained in the peripheral circuit modules, and a first power switch for controlling supply of a current to the first area. When the information processing device operates in a first mode, an operating current is supplied to the first area and the second area. When the information processing device operates in a second mode, the first power switch is controlled so that the supply of the current to the first area can be shut off, and the supply of the current to the second area is continued.
摘要翻译：实现了由与中断引起的来自待机的快速返回操作兼容的断电引起的低待机电流的机制。信息处理装置具有包括中央处理单元和外围电路模块的第一区域，具有用于保持包含在外围电路模块中的寄存器的值的信息保持电路的第二区域和用于控制向外部电路提供电流的第一电源开关第一个区域。当信息处理装置以第一模式操作时，工作电流被提供给第一区域和第二区域。当信息处理装置在第二模式下操作时，控制第一电源开关，使得可以切断对第一区域的电流的供应，并且继续向第二区域供应电流。

5. 发明授权

US07493479B2 Method and apparatus for event detection for multiple instruction-set processor 有权
标题翻译：多指令集处理器的事件检测方法和装置
公开(公告)号：US07493479B2
公开(公告)日：2009-02-17
申请号：US10458289
申请日：2003-06-11
申请人： Masayuki Kabasawa , Naohiko Irie , Takahiro Irita , Tetsuya Yamada , Takanobu Tsunoda
发明人： Masayuki Kabasawa , Naohiko Irie , Takahiro Irita , Tetsuya Yamada , Takanobu Tsunoda
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00 , G06F7/38
CPC分类号： G06F9/30174 , G06F9/3851
摘要： A method and apparatus are provided for event detection for a multiple instruction-set processor. In one example of the apparatus, a data processing device comprises an instruction execution device configured to execute a first instruction set as specific instructions; an instruction conversion circuit configured to convert instructions of a second instruction set into a first instruction string of the first instruction set, and further configured to supply the first instruction string to the instruction execution device; and a counter device configured to count a prescribed event, wherein the instruction conversion circuit is further configured to output a prescribed instruction when the counter device is satisfied by a prescribed condition.
摘要翻译：提供了一种用于多指令集处理器的事件检测的方法和装置。在该装置的一个示例中，数据处理装置包括被配置为执行第一指令集作为特定指令的指令执行装置; 指令转换电路，被配置为将第二指令集的指令转换为第一指令集的第一指令串，并且还被配置为将第一指令串提供给指令执行装置; 以及计数器装置，被配置为对规定的事件进行计数，其中所述指令转换电路还被配置为当所述计数器装置满足规定条件时输出规定的指令。

6. 发明授权

US07340078B2 Multi-sensing devices cooperative recognition system 失效
标题翻译：多感器设备协同识别系统
公开(公告)号：US07340078B2
公开(公告)日：2008-03-04
申请号：US10876596
申请日：2004-06-28
申请人： Hiroaki Shikano , Naohiko Irie
发明人： Hiroaki Shikano , Naohiko Irie
IPC分类号： G06K9/00
CPC分类号： G06K9/00664
摘要： Disclosed here is an information processing system capable of recognizing actions and circumstances of a user with respect to both space and time as a “situation” to recognize the user's request using a plurality of sensing nodes that work cooperatively with each another, thereby responding autonomously to the user's request according to the recognition results. The plurality of sensing nodes and a responding device are disposed in a target space to build up a network for recognizing the situation in the target space. And, a plurality of recognition means are used to recognize the situation with respect to both space and time related to the existence of the user. And, an integral processing portion (master) is selected from among the plurality of sensing nodes, thereby dispersing the system load. If there are a plurality of users, the system can make recognition in accordance with the request of each of those users.
摘要翻译：这里公开了一种信息处理系统，其能够将用户相对于空间和时间的动作和情况识别为使用多个彼此协作工作的感测节点来识别用户的请求的“情况”，从而自主地响应于用户的请求根据识别结果。多个感测节点和响应装置设置在目标空间中以构建用于识别目标空间中的情况的网络。并且，使用多个识别装置来识别与用户的存在相关的空间和时间的情况。并且，从多个感测节点中选择积分处理部（主），从而分散系统负载。如果存在多个用户，则系统可以根据每个用户的请求进行识别。

7. 发明申请

US20070284619A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20070284619A1
公开(公告)日：2007-12-13
申请号：US11797034
申请日：2007-04-30
申请人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
发明人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
IPC分类号： H01L29/73
CPC分类号： G01R31/318572 , G11C5/063 , G11C11/417 , H01L27/0207 , H01L27/092 , H01L27/11807 , H01L2924/0002 , H03K3/356008 , H03K3/35625 , H03K19/0016 , H01L2924/00
摘要： In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.
摘要翻译：在功率关闭时保留先前数据的低功耗模式下，其返回速度增加。虽然可以考虑使用现有的数据保持触发器，但是这不是优选的，因为它增加了诸如扩大单元大小的面积开销。用于电源关闭的数据保持的电源线由比通常的主电源线更细的布线形成。优选地，用于数据保持电路的电力线被认为是信号线，并通过自动放置和安装进行布线。为此，先前通过以与现有信号线相同的方式为小区提供终端来设计用于数据保持的电力线的终端。电池线的附加布局不再需要，这使得现有的放置和布线工具能够减少面积和设计。

8. 发明申请

US20060146635A1 Semiconductor device 有权
公开(公告)号：US20060146635A1
公开(公告)日：2006-07-06
申请号：US11363060
申请日：2006-02-28
申请人： Takao Watanabe , Kunio Uchiyama , Osamu Nishii , Naohiko Irie , Hiroyuki Mizuno
发明人： Takao Watanabe , Kunio Uchiyama , Osamu Nishii , Naohiko Irie , Hiroyuki Mizuno
IPC分类号： G11C5/14
CPC分类号： G06F1/3203 , G06F1/3287 , G11C5/147 , G11C11/417 , Y02D10/171
摘要： When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

9. 发明申请

US20050027965A1 Information processing device 失效
标题翻译：信息处理装置
公开(公告)号：US20050027965A1
公开(公告)日：2005-02-03
申请号：US10883758
申请日：2004-07-06
申请人： Tetsuya Yamada , Naohiko Irie , Takahiro Irita , Masayuki Kabasawa
发明人： Tetsuya Yamada , Naohiko Irie , Takahiro Irita , Masayuki Kabasawa
IPC分类号： G06F9/38 , G06F9/30 , G06F9/302 , G06F9/318 , G06F9/45 , G06F15/00
CPC分类号： G06F9/30174 , G06F9/30014 , G06F9/3861 , G06F9/3877 , G06F9/3879
摘要： A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when 4corresponding data is detected in a data checking part.
摘要翻译：硬件加速器用于在信息处理设备中执行浮点字节码。对于浮点字节码，字节码加速器BCA将用于使用FPU的指令流馈送到CPU。当使用FPU时，首先将数据从通用寄存器传送到FPU寄存器，然后执行FPU操作。对于不能由FPU处理的数据，如非规范化数字，为了调用软件的浮点数学库，BCA的处理完成，并且处理转移到软件处理。为了实现这一点，由硬件加速器监视从CPU到FPU的数据传输总线上的数据，并且当在数据检查中检测到4个对应数据时，向CPU发送取消请求以禁止执行FPU操作部分。

10. 发明授权

US07814343B2 Semiconductor integrated circuit for reducing power consumption and enhancing processing speed 失效
标题翻译：半导体集成电路，用于降低功耗并提高处理速度
公开(公告)号：US07814343B2
公开(公告)日：2010-10-12
申请号：US11605362
申请日：2006-11-29
申请人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
发明人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06F12/00
CPC分类号： G06F1/3293 , G06F1/3203 , H01L21/823462 , Y02D10/122 , Y02D10/126
摘要： A semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device includes thermal sensors which detect temperature and determine whether the detection result exceeds reference values and output the result, and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors. The control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.
摘要翻译：一种半导体集成电路器件，其消耗较少功率并实现实时处理。半导体集成电路装置包括检测温度并确定检测结果是否超过参考值并输出结果的热传感器，以及能够基于热传感器的输出信号来控制运算块的操作的控制块。控制块基于热传感器的输出信号从具有中断信号的挂起状态返回到操作状态，并且确定运算块的操作条件，以确保运算块的温度条件得到满足。从而降低了功耗，提高了实时处理效率。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式