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1. 发明授权

US07124283B2 Hardware accelerator for a platform-independent code 有权
标题翻译：硬件加速器，用于与平台无关的代码
公开(公告)号：US07124283B2
公开(公告)日：2006-10-17
申请号：US10457409
申请日：2003-06-10
申请人： Tetsuya Yamada , Naohiko Irie , Takanobu Tsunoda , Takahiro Irita , Keisuke Toyama , Masayuki Kabasawa
发明人： Tetsuya Yamada , Naohiko Irie , Takanobu Tsunoda , Takahiro Irita , Keisuke Toyama , Masayuki Kabasawa
IPC分类号： G06F5/00
CPC分类号： G06F9/3879 , G06F9/30174 , G06F9/4552
摘要： The present invention provides a hardware accelerator, which allows faster switching between processing modes. In an information processing device with a bytecode accelerator BCA for translating a stack-based intermediate code (bytecode) into register-based instructions, a selector SEL for switching between BCA and soft VM is posed between an instruction part FET and a decode part DEC and data transfer paths P4 and P5 are formed between BCA and the register file REG_FILE. When bytecode accelerator BCA is activated, the P3 side is selected by the selector SEL and the translated CPU instructions are transferred to the decode part DEC. If the intermediate language code cannot be translated by the BCA, the processing mode is switched to software processing. During switching between the modes, internal information of BCA can be transferred between BCA and REG_FILE in parallel, achieving faster mode switching.
摘要翻译：本发明提供一种硬件加速器，其允许在处理模式之间更快地切换。在具有用于将基于堆栈的中间码（字节码）转换为基于寄存器的指令的字节码加速器BCA的信息处理装置中，在指令部分FET和解码部分DEC之间存在用于在BCA和软VM之间切换的选择器SEL，在BCA和寄存器文件REG_FILE之间形成数据传送路径P 4和P 5。当字节码加速器BCA被激活时，选择器SEL选择P 3侧，转换的CPU指令被传送到解码部分DEC。如果BCA不能翻译中间语言代码，则将处理模式切换到软件处理。在模式切换期间，BCA的内部信息可以在BCA和REG_FILE之间并行传输，实现更快的模式切换。

2. 发明授权

US07788469B2 Information processing device having arrangements to inhibit coprocessor upon encountering data that the coprocessor cannot handle 失效
标题翻译：信息处理装置具有在遇到协处理器不能处理的数据时禁止协处理器的装置
公开(公告)号：US07788469B2
公开(公告)日：2010-08-31
申请号：US10883758
申请日：2004-07-06
申请人： Tetsuya Yamada , Naohiko Irie , Takahiro Irita , Masayuki Kabasawa
发明人： Tetsuya Yamada , Naohiko Irie , Takahiro Irita , Masayuki Kabasawa
IPC分类号： G06F15/76
CPC分类号： G06F9/30174 , G06F9/30014 , G06F9/3861 , G06F9/3877 , G06F9/3879
摘要： A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when corresponding data is detected in a data checking part.
摘要翻译：硬件加速器用于在信息处理设备中执行浮点字节码。对于浮点字节码，字节码加速器BCA将用于使用FPU的指令流馈送到CPU。当使用FPU时，首先将数据从通用寄存器传送到FPU寄存器，然后执行FPU操作。对于不能由FPU处理的数据，如非规范化数字，为了调用软件的浮点数学库，BCA的处理完成，并且处理转移到软件处理。为了实现这一点，由硬件加速器窥探从CPU到FPU的数据传输总线上的数据，并且当在数据检查中检测到对应的数据时，向CPU发送取消请求以禁止执行FPU操作部分。

3. 发明授权

US07493479B2 Method and apparatus for event detection for multiple instruction-set processor 有权
标题翻译：多指令集处理器的事件检测方法和装置
公开(公告)号：US07493479B2
公开(公告)日：2009-02-17
申请号：US10458289
申请日：2003-06-11
申请人： Masayuki Kabasawa , Naohiko Irie , Takahiro Irita , Tetsuya Yamada , Takanobu Tsunoda
发明人： Masayuki Kabasawa , Naohiko Irie , Takahiro Irita , Tetsuya Yamada , Takanobu Tsunoda
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00 , G06F7/38
CPC分类号： G06F9/30174 , G06F9/3851
摘要： A method and apparatus are provided for event detection for a multiple instruction-set processor. In one example of the apparatus, a data processing device comprises an instruction execution device configured to execute a first instruction set as specific instructions; an instruction conversion circuit configured to convert instructions of a second instruction set into a first instruction string of the first instruction set, and further configured to supply the first instruction string to the instruction execution device; and a counter device configured to count a prescribed event, wherein the instruction conversion circuit is further configured to output a prescribed instruction when the counter device is satisfied by a prescribed condition.
摘要翻译：提供了一种用于多指令集处理器的事件检测的方法和装置。在该装置的一个示例中，数据处理装置包括被配置为执行第一指令集作为特定指令的指令执行装置; 指令转换电路，被配置为将第二指令集的指令转换为第一指令集的第一指令串，并且还被配置为将第一指令串提供给指令执行装置; 以及计数器装置，被配置为对规定的事件进行计数，其中所述指令转换电路还被配置为当所述计数器装置满足规定条件时输出规定的指令。

4. 发明申请

US20050027965A1 Information processing device 失效
标题翻译：信息处理装置
公开(公告)号：US20050027965A1
公开(公告)日：2005-02-03
申请号：US10883758
申请日：2004-07-06
申请人： Tetsuya Yamada , Naohiko Irie , Takahiro Irita , Masayuki Kabasawa
发明人： Tetsuya Yamada , Naohiko Irie , Takahiro Irita , Masayuki Kabasawa
IPC分类号： G06F9/38 , G06F9/30 , G06F9/302 , G06F9/318 , G06F9/45 , G06F15/00
CPC分类号： G06F9/30174 , G06F9/30014 , G06F9/3861 , G06F9/3877 , G06F9/3879
摘要： A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when 4corresponding data is detected in a data checking part.
摘要翻译：硬件加速器用于在信息处理设备中执行浮点字节码。对于浮点字节码，字节码加速器BCA将用于使用FPU的指令流馈送到CPU。当使用FPU时，首先将数据从通用寄存器传送到FPU寄存器，然后执行FPU操作。对于不能由FPU处理的数据，如非规范化数字，为了调用软件的浮点数学库，BCA的处理完成，并且处理转移到软件处理。为了实现这一点，由硬件加速器监视从CPU到FPU的数据传输总线上的数据，并且当在数据检查中检测到4个对应数据时，向CPU发送取消请求以禁止执行FPU操作部分。

5. 发明授权

US07853776B2 Handover between software and hardware accelerator 有权
标题翻译：软件和硬件加速器之间切换
公开(公告)号：US07853776B2
公开(公告)日：2010-12-14
申请号：US11260423
申请日：2005-10-28
申请人： Tetsuya Yamada , Naohiko Irie
发明人： Tetsuya Yamada , Naohiko Irie
IPC分类号： G06F9/30
CPC分类号： G06F9/30174
摘要： A bytecode accelerator which translates stack-based intermediate language (bytecodes) into register-based CPU instructions transfers plural pieces of internal information from a register file of a CPU to the bytecode accelerator by means of an internal transfer bus between the bytecode accelerator and the CPU and an input selection logic of the bytecode accelerator when the bytecode accelerator is started and transfers plural pieces of internal information in the bytecode accelerator to the register file of the CPU by means of the internal transfer bus, an output selector and an output selector selection logic of the bytecode accelerator when the bytecode accelerator ends its operation in transition between hardware processing and software processing by software virtual machine.
摘要翻译：将基于堆栈的中间语言（字节码）转换为基于寄存器的CPU指令的字节码加速器通过字节码加速器和CPU之间的内部传输总线将多条内部信息从CPU的寄存器文件传送到字节码加速器以及当字节代码加速器启动时字节码加速器的输入选择逻辑，并且通过内部传送总线，输出选择器和输出选择器选择逻辑，将字节码加速器中的多条内部信息传送到CPU的寄存器文件字节码加速器在硬件处理和软件虚拟机的软件处理之间的转换中结束其操作。

6. 发明申请

US20060101427A1 Handover between software and hardware accelarator 有权
标题翻译：软硬件加速器之间切换
公开(公告)号：US20060101427A1
公开(公告)日：2006-05-11
申请号：US11260423
申请日：2005-10-28
申请人： Tetsuya Yamada , Naohiko Irie
发明人： Tetsuya Yamada , Naohiko Irie
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F9/30174
摘要： A bytecode accelerator which translates stack-based intermediate language (bytecodes) into register-based CPU instructions transfers plural pieces of internal information from a register file of a CPU to the bytecode accelerator by means of an internal transfer bus between the bytecode accelerator-and the CPU and an input selection logic of the bytecode accelerator when the bytecode accelerator is started and transfers plural pieces of internal information in the bytecode accelerator to the register file of the CPU by means of the internal transfer bus, an output selector and an output selector selection logic of the bytecode accelerator when the bytecode accelerator ends its operation in transition between hardware processing and software processing by software virtual machine.
摘要翻译：将基于堆栈的中间语言（字节码）转换为基于寄存器的CPU指令的字节码加速器通过字节码加速器和字节码加速器之间的内部传送总线将多条内部信息从CPU的寄存器文件传送到字节码加速器 CPU和字节码加速器的输入选择逻辑，并且通过内部传送总线，输出选择器和输出选择器选择将字节码加速器中的多条内部信息传送到CPU的寄存器文件字节码加速器在硬件处理和软件虚拟机的软件处理之间的转换中结束其操作时，字节码加速器的逻辑。

7. 发明授权

US09606902B2 Malfunction influence evaluation system and evaluation method using a propagation flag 有权
公开(公告)号：US09606902B2
公开(公告)日：2017-03-28
申请号：US14404844
申请日：2012-07-03
申请人： Akihiko Hyodo , Yasuo Sugure , Yasuhiro Ito , Tetsuya Yamada
发明人： Akihiko Hyodo , Yasuo Sugure , Yasuhiro Ito , Tetsuya Yamada
IPC分类号： G06F11/36 , G05B19/042 , G05B23/02
CPC分类号： G06F11/3688 , G05B19/0428 , G05B23/0213 , G06F11/3636 , G06F11/3644 , G06F11/3664
摘要： Provided is a malfunction influence evaluation system comprising a controller simulator that simulates the operation of a controller, an input apparatus that provides input data to the controller simulator, a simulation manager that exercises integrated management of the operation of the input apparatus and the controller simulator, and a database wherein malfunction information and simulation conditions to be referred to by the simulation manager is stored. The controller simulator retains a control program for the controller and an analysis unit, and the analysis unit has a propagation flag tracking function wherein propagation flags are assigned to a variable within the control program, bits of the variable are set by inputting a prescribed value thereto as a malfunction input value, the bits are propagated each time the variable is involved in a calculation within the control program, the states of propagation of the bits are tracked, and the result thereof is output.

8. 发明授权

US09246320B2 Motor-driven compressor 有权
标题翻译：电动压缩机
公开(公告)号：US09246320B2
公开(公告)日：2016-01-26
申请号：US13251425
申请日：2011-10-03
申请人： Tetsuya Yamada , Ken Suitou , Shingo Enami , Akio Fujii
发明人： Tetsuya Yamada , Ken Suitou , Shingo Enami , Akio Fujii
IPC分类号： H02G15/013 , F04B35/04 , F04B39/12 , F04C23/00 , F04C18/02
CPC分类号： H02G15/013 , F04B35/04 , F04B39/12 , F04B39/121 , F04C18/0215 , F04C23/008 , F04C2240/803
摘要： A motor-driven compressor includes a shell, an electric motor, a first conductor electrically connected to an external power source, a second conductor electrically connected to the electric motor, a connector connecting the first conductor and the second conductor and a connector case. The connector case has a first case member, a second case member, a first and a second seal members interposed between the first and the second case members, a hole through which the first conductor is inserted and a third seal member sealing between the first conductor and the connector case. A first main seal of the first seal member and a second main seal of the second seal member cooperate to form a cylindrical seal portion for sealing the second conductor that is inserted through the cylindrical seal portion when the first and the second seal members are joined.
摘要翻译：电动压缩机包括外壳，电动马达，电连接到外部电源的第一导体，电连接到电动机的第二导体，连接第一导体和第二导体的连接器以及连接器壳体。连接器壳体具有第一壳体构件，第二壳体构件，插入在第一和第二壳体构件之间的第一和第二密封构件，插入第一导体的孔和密封在第一导体之间的第三密封构件和连接器盒。第一密封构件的第一主密封件和第二密封构件的第二主密封件协作以形成圆柱形密封部分，用于在第一和第二密封构件接合时密封插入通过圆柱形密封部分的第二导体。

9. 发明申请

US20150006000A1 CONTROL SYSTEM AND CONTROL METHOD FOR HYBRID VEHICLE 审中-公开
标题翻译：混合车辆的控制系统和控制方法
公开(公告)号：US20150006000A1
公开(公告)日：2015-01-01
申请号：US14241398
申请日：2012-09-05
申请人： Kohei Kawata , Takashi Kon , Masahiro Takeuchi , Shigetaka Kuroda , Yuki Honma , Tetsuya Yamada , Kentaro Yokoo
发明人： Kohei Kawata , Takashi Kon , Masahiro Takeuchi , Shigetaka Kuroda , Yuki Honma , Tetsuya Yamada , Kentaro Yokoo
IPC分类号： B60W20/00 , B60W10/06 , B60W10/26 , B60W10/08 , B60W10/10
CPC分类号： B60W20/13 , B60K6/48 , B60K6/547 , B60L7/14 , B60L15/2045 , B60L15/2054 , B60L58/13 , B60L2240/12 , B60L2240/507 , B60L2240/545 , B60L2240/547 , B60L2240/549 , B60L2240/622 , B60L2250/26 , B60L2260/50 , B60L2260/54 , B60W10/06 , B60W10/08 , B60W10/10 , B60W10/113 , B60W10/26 , B60W20/00 , B60W20/14 , B60W20/30 , B60W20/40 , B60W30/18127 , B60W2710/083 , B60W2710/1005 , H02P9/06 , Y02T10/6221 , Y02T10/645 , Y02T10/7005 , Y02T10/7044 , Y02T10/705 , Y02T10/72 , Y02T10/7283 , Y02T10/7291 , Y02T90/16 , Y02T90/162 , Y10S903/93
摘要： A control system and control method for a hybrid vehicle, which properly determine based on a predicted charge amount whether or not to change a speed position, to thereby obtain a larger charge amount, thereby making it possible enhance fuel economy of the hybrid vehicle. A first charge amount is estimated which is an amount of electric power charged into a storage battery when regeneration is performed by an electric motor in a state in which the speed position of a stepped transmission is held, for a predetermined regeneration time period. Further, a second charge amount is estimated which is an amount of electric power charged into the storage battery when the speed position is changed to a target speed position within the regeneration time period, and regeneration by the electric motor 4 is performed until the regeneration time period elapses.
摘要翻译：一种用于混合动力车辆的控制系统和控制方法，其基于预测的充电量来适当地确定是否改变速度位置，从而获得较大的充电量，从而可以提高混合动力车辆的燃料经济性。估计第一充电量，其为在保持阶梯式变速器的速度位置的状态下通过电动机进行再生而在预定的再生时间段内充入蓄电池的电力的量。此外，估计第二充电量，其是当在再生时间段内将速度位置改变为目标速度位置时，充电到蓄电池中的电力量，并且执行电动机4的再生直到再生时间时间过去了。

10. 发明授权

US08865546B2 Method for manufacturing a non-volatile semiconductor memory device having contact plug formed on silicided source/drain region 有权
标题翻译：用于制造具有形成在硅化物源极/漏极区域上的接触插塞的非易失性半导体存储器件的方法
公开(公告)号：US08865546B2
公开(公告)日：2014-10-21
申请号：US13616806
申请日：2012-09-14
申请人： Tetsuya Yamada
发明人： Tetsuya Yamada
IPC分类号： H01L21/336 , H01L29/66 , H01L21/311 , H01L27/115 , H01L29/788 , H01L21/316 , H01L21/285 , H01L27/105 , G11C16/04 , H01L27/02
CPC分类号： H01L29/66825 , G11C16/0433 , H01L21/28518 , H01L21/31144 , H01L21/3165 , H01L21/31662 , H01L27/0207 , H01L27/105 , H01L27/11517 , H01L27/11526 , H01L27/11529 , H01L29/7883
摘要： A method for manufacturing a semiconductor device includes the steps of forming a flash memory cell provided with a floating gate, an intermediate insulating film, and a control gate, forming first and second impurity diffusion regions, thermally oxidizing surfaces of a silicon substrate and the floating gate, etching a tunnel insulating film in a partial region through a window of a resist pattern; forming a metal silicide layer on the first impurity diffusion region in the partial region, forming an interlayer insulating film covering the flash memory cell, and forming, in a first hole of the interlayer insulating film, a conductive plug connected to the metal silicide layer.
摘要翻译：一种制造半导体器件的方法包括以下步骤：形成设置有浮置栅极，中间绝缘膜和控制栅极的闪速存储单元，形成第一和第二杂质扩散区，热氧化硅衬底的表面和浮置栅极，通过抗蚀剂图案的窗口蚀刻部分区域中的隧道绝缘膜; 在所述部分区域中的所述第一杂质扩散区上形成金属硅化物层，形成覆盖所述闪速存储单元的层间绝缘膜，以及在所述层间绝缘膜的第一孔中形成与所述金属硅化物层连接的导电插塞。

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