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1. 发明授权

US07340078B2 Multi-sensing devices cooperative recognition system 失效
标题翻译：多感器设备协同识别系统
公开(公告)号：US07340078B2
公开(公告)日：2008-03-04
申请号：US10876596
申请日：2004-06-28
申请人： Hiroaki Shikano , Naohiko Irie
发明人： Hiroaki Shikano , Naohiko Irie
IPC分类号： G06K9/00
CPC分类号： G06K9/00664
摘要： Disclosed here is an information processing system capable of recognizing actions and circumstances of a user with respect to both space and time as a “situation” to recognize the user's request using a plurality of sensing nodes that work cooperatively with each another, thereby responding autonomously to the user's request according to the recognition results. The plurality of sensing nodes and a responding device are disposed in a target space to build up a network for recognizing the situation in the target space. And, a plurality of recognition means are used to recognize the situation with respect to both space and time related to the existence of the user. And, an integral processing portion (master) is selected from among the plurality of sensing nodes, thereby dispersing the system load. If there are a plurality of users, the system can make recognition in accordance with the request of each of those users.
摘要翻译：这里公开了一种信息处理系统，其能够将用户相对于空间和时间的动作和情况识别为使用多个彼此协作工作的感测节点来识别用户的请求的“情况”，从而自主地响应于用户的请求根据识别结果。多个感测节点和响应装置设置在目标空间中以构建用于识别目标空间中的情况的网络。并且，使用多个识别装置来识别与用户的存在相关的空间和时间的情况。并且，从多个感测节点中选择积分处理部（主），从而分散系统负载。如果存在多个用户，则系统可以根据每个用户的请求进行识别。

2. 发明授权

US07454216B2 in-facility information provision system and in-facility information provision method 失效
标题翻译：设施内信息提供系统和设施信息提供方法
公开(公告)号：US07454216B2
公开(公告)日：2008-11-18
申请号：US11071342
申请日：2005-03-04
申请人： Hiroaki Shikano , Naohiko Irie , Atsushi Ito , Junji Inaba , Mitsuru Inoue , Kazutaka Sakai
发明人： Hiroaki Shikano , Naohiko Irie , Atsushi Ito , Junji Inaba , Mitsuru Inoue , Kazutaka Sakai
IPC分类号： H04Q7/20
CPC分类号： G06Q30/00
摘要： To enable an appropriate change of a path according to a situation of a user and a situation of a target store and the path without having a special terminal when the user of a facility utilizes the target store and an appropriate guidance, spatial recognition nodes respectively provided with a sensor and information processing equipment are installed in each location in the facility and connected via a network. The nodes recognize the position, the action and the behavior of a user of the facility. A server controlling a system manages the recognition result and constantly grasps the situation of the user. The situation of the user is recognized by the node installed at a destination and on a path, and notified to the server. The server displays appropriate path information based on the recognition result on any of plural information displays installed in the facility when the user approaches.
摘要翻译：为了在设施的用户利用目标存储和适当的指导的情况下，根据用户的情况和目标存储的情况以及路径而不具有特殊终端的路径的适当改变，分别提供了空间识别节点传感器和信息处理设备安装在设施的每个位置并通过网络连接。节点识别设施的用户的位置，动作和行为。控制系统的服务器管理识别结果并且不断掌握用户的情况。用户的情况由安装在目的地和路径上的节点识别，并通知给服务器。当用户接近时，服务器基于在设施中安装的多个信息显示器中的任一个上的识别结果来显示适当的路径信息。

3. 发明申请

US20060085582A1 Multiprocessor system 审中-公开
标题翻译：多处理器系统
公开(公告)号：US20060085582A1
公开(公告)日：2006-04-20
申请号：US11203284
申请日：2005-08-15
申请人： Hiroaki Shikano , Naohiko Irie
发明人： Hiroaki Shikano , Naohiko Irie
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： An interrupt notification network is provided for a multiprocessor system in which many processor units are installed. An interrupt notification source processor unit transmits an interrupt notification packet to an interrupt notification destination processor unit. The interrupt notification packet to be transmitted by the interrupt notification source processor unit contains an interrupt destination process ID. A control section for the interrupt notification network analyzes the transmitted interrupt notification packet, references a table that defines the correspondence between internally retained IDs of processes and processor units that perform the processes, determines the interrupt notification destination processor unit, and transmits the interrupt notification packet to the processor unit. Consequently, the multiprocessor system in which many processor units are installed is capable of performing an inter-processor unit multiplex coordination process for inter-processor unit process synchronization and process control, increasing the system throughput, and providing increased real-time capability.
摘要翻译：为其中安装许多处理器单元的多处理器系统提供中断通知网络。中断通知源处理器单元向中断通知目的地处理器单元发送中断通知分组。要由中断通知源处理器单元发送的中断通知包含有中断目的地处理ID。用于中断通知网络的控制部分分析发送的中断通知分组，引用定义进程的内部保留ID和处理器单元之间的对应关系的表，确定中断通知目的地处理器单元，并发送中断通知分组到处理器单元。因此，其中安装有许多处理器单元的多处理器系统能够执行用于处理器间单元处理同步和过程控制的处理器间单元复用协调处理，增加系统吞吐量并提供增加的实时能力。

4. 发明申请

US20060040679A1 In-facility information provision system and in-facility information provision method 失效
标题翻译：设施内信息提供系统和设施信息提供方法
公开(公告)号：US20060040679A1
公开(公告)日：2006-02-23
申请号：US11071342
申请日：2005-03-04
申请人： Hiroaki Shikano , Naohiko Irie , Atsushi Ito , Junji Inaba , Mitsuru Inoue , Kazutaka Sakai
发明人： Hiroaki Shikano , Naohiko Irie , Atsushi Ito , Junji Inaba , Mitsuru Inoue , Kazutaka Sakai
IPC分类号： H04Q7/20
CPC分类号： G06Q30/00
摘要： The object of the invention is to enable the appropriate change of a path according to a situation at that time of a user himself/herself and a situation of a target store and the path without having a special terminal when the user of facilities utilizes the target store and to perform appropriate guidance. To achieve the object, first, plural spatial recognition nodes respectively provided with a sensor and information processing equipment are installed in each location in the facilities and are connected via a network. The node recognizes the position, the action and the behavior of a user of the facilities, a server that controls a system manages the result of recognition and constantly grasp the situation of the user. Besides, the situation of the user is recognized by the node installed at a destination and on a path and is similarly notified to the server. The server displays appropriate path information based on the result of recognition on any of plural information displays installed in the facilities when the user approaches.
摘要翻译：本发明的目的是当设施的用户利用目标时，能够根据用户自身当时的情况和目标存储的情况以及路径的适当改变，而不具有特殊的终端存储并执行适当的指导。为了实现该目的，首先，分别设置有传感器和信息处理设备的多个空间识别节点安装在设施的每个位置，并经由网络连接。节点识别设施的用户的位置，动作和行为，控制系统的服务器管理识别结果并且不断掌握用户的情况。此外，用户的情况被安装在目的地和路径上的节点识别，并且被类似地通知给服务器。当用户接近时，服务器基于在设施中安装的多个信息显示中的任一个上的识别结果来显示适当的路径信息。

5. 发明申请

US20050078854A1 Multi-sensing devices cooperative recognition system 失效
标题翻译：多感器设备协同识别系统
公开(公告)号：US20050078854A1
公开(公告)日：2005-04-14
申请号：US10876596
申请日：2004-06-28
申请人： Hiroaki Shikano , Naohiko Irie
发明人： Hiroaki Shikano , Naohiko Irie
IPC分类号： G06K9/00 , G06K9/68 , G06Q50/00 , G06Q50/10 , G06T7/20 , H04N7/18
CPC分类号： G06K9/00664
摘要： Disclosed here is an information processing system capable of recognizing actions and circumstances of a user with respect to both space and time as a “situation” to recognize the user's request using a plurality of sensing nodes that work cooperatively with each another, thereby responding autonomously to the user's request according to the recognition results. The plurality of sensing nodes and a responding device are disposed in a target space to build up a network for recognizing the situation in the target space. And, a plurality of recognition means are used to recognize the situation with respect to both space and time related to the existence of the user. And, an integral processing portion (master) is selected from among the plurality of sensing nodes, thereby dispersing the system load. If there are a plurality of users, the system can make recognition in accordance with the request of each of those users.
摘要翻译：这里公开了一种信息处理系统，其能够将用户相对于空间和时间的动作和情况识别为使用多个彼此协作工作的感测节点来识别用户的请求的“情况”，从而自主地响应于用户的请求根据识别结果。多个感测节点和响应装置设置在目标空间中以构建用于识别目标空间中的情况的网络。并且，使用多个识别装置来识别与用户的存在相关的空间和时间的情况。并且，从多个感测节点中选择积分处理部（主），从而分散系统负载。如果存在多个用户，则系统可以根据每个用户的请求进行识别。

6. 发明授权

US07493479B2 Method and apparatus for event detection for multiple instruction-set processor 有权
标题翻译：多指令集处理器的事件检测方法和装置
公开(公告)号：US07493479B2
公开(公告)日：2009-02-17
申请号：US10458289
申请日：2003-06-11
申请人： Masayuki Kabasawa , Naohiko Irie , Takahiro Irita , Tetsuya Yamada , Takanobu Tsunoda
发明人： Masayuki Kabasawa , Naohiko Irie , Takahiro Irita , Tetsuya Yamada , Takanobu Tsunoda
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00 , G06F7/38
CPC分类号： G06F9/30174 , G06F9/3851
摘要： A method and apparatus are provided for event detection for a multiple instruction-set processor. In one example of the apparatus, a data processing device comprises an instruction execution device configured to execute a first instruction set as specific instructions; an instruction conversion circuit configured to convert instructions of a second instruction set into a first instruction string of the first instruction set, and further configured to supply the first instruction string to the instruction execution device; and a counter device configured to count a prescribed event, wherein the instruction conversion circuit is further configured to output a prescribed instruction when the counter device is satisfied by a prescribed condition.
摘要翻译：提供了一种用于多指令集处理器的事件检测的方法和装置。在该装置的一个示例中，数据处理装置包括被配置为执行第一指令集作为特定指令的指令执行装置; 指令转换电路，被配置为将第二指令集的指令转换为第一指令集的第一指令串，并且还被配置为将第一指令串提供给指令执行装置; 以及计数器装置，被配置为对规定的事件进行计数，其中所述指令转换电路还被配置为当所述计数器装置满足规定条件时输出规定的指令。

7. 发明申请

US20070284619A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20070284619A1
公开(公告)日：2007-12-13
申请号：US11797034
申请日：2007-04-30
申请人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
发明人： Yusuke Kanno , Hiroyuki Mizuno , Naohiko Irie
IPC分类号： H01L29/73
CPC分类号： G01R31/318572 , G11C5/063 , G11C11/417 , H01L27/0207 , H01L27/092 , H01L27/11807 , H01L2924/0002 , H03K3/356008 , H03K3/35625 , H03K19/0016 , H01L2924/00
摘要： In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.
摘要翻译：在功率关闭时保留先前数据的低功耗模式下，其返回速度增加。虽然可以考虑使用现有的数据保持触发器，但是这不是优选的，因为它增加了诸如扩大单元大小的面积开销。用于电源关闭的数据保持的电源线由比通常的主电源线更细的布线形成。优选地，用于数据保持电路的电力线被认为是信号线，并通过自动放置和安装进行布线。为此，先前通过以与现有信号线相同的方式为小区提供终端来设计用于数据保持的电力线的终端。电池线的附加布局不再需要，这使得现有的放置和布线工具能够减少面积和设计。

8. 发明申请

US20060146635A1 Semiconductor device 有权
公开(公告)号：US20060146635A1
公开(公告)日：2006-07-06
申请号：US11363060
申请日：2006-02-28
申请人： Takao Watanabe , Kunio Uchiyama , Osamu Nishii , Naohiko Irie , Hiroyuki Mizuno
发明人： Takao Watanabe , Kunio Uchiyama , Osamu Nishii , Naohiko Irie , Hiroyuki Mizuno
IPC分类号： G11C5/14
CPC分类号： G06F1/3203 , G06F1/3287 , G11C5/147 , G11C11/417 , Y02D10/171
摘要： When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

9. 发明申请

US20050027965A1 Information processing device 失效
标题翻译：信息处理装置
公开(公告)号：US20050027965A1
公开(公告)日：2005-02-03
申请号：US10883758
申请日：2004-07-06
申请人： Tetsuya Yamada , Naohiko Irie , Takahiro Irita , Masayuki Kabasawa
发明人： Tetsuya Yamada , Naohiko Irie , Takahiro Irita , Masayuki Kabasawa
IPC分类号： G06F9/38 , G06F9/30 , G06F9/302 , G06F9/318 , G06F9/45 , G06F15/00
CPC分类号： G06F9/30174 , G06F9/30014 , G06F9/3861 , G06F9/3877 , G06F9/3879
摘要： A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when 4corresponding data is detected in a data checking part.
摘要翻译：硬件加速器用于在信息处理设备中执行浮点字节码。对于浮点字节码，字节码加速器BCA将用于使用FPU的指令流馈送到CPU。当使用FPU时，首先将数据从通用寄存器传送到FPU寄存器，然后执行FPU操作。对于不能由FPU处理的数据，如非规范化数字，为了调用软件的浮点数学库，BCA的处理完成，并且处理转移到软件处理。为了实现这一点，由硬件加速器监视从CPU到FPU的数据传输总线上的数据，并且当在数据检查中检测到4个对应数据时，向CPU发送取消请求以禁止执行FPU操作部分。

10. 发明授权

US08122233B2 Information processing device 有权
标题翻译：信息处理装置
公开(公告)号：US08122233B2
公开(公告)日：2012-02-21
申请号：US12124232
申请日：2008-05-21
申请人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
发明人： Motokazu Ozawa , Naohiko Irie , Saneaki Tamaki , Hisayoshi Ide , Miki Hayakawa
IPC分类号： G06F9/00 , G06F15/177
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： An information processing device, including: a processing unit; a peripheral circuit module; and a boot address register, wherein the information processing device comprises a first operation mode and a second operation mode having an operating current which is lower than that of said first operation mode, wherein the boot address register holds an address of an instruction to be executed by said processing unit first when the boot address register returns from said second operation mode to said first operation mode, wherein the address is output from said boot address to the processing unit when said information processing device shifts from said second operation mode to said first operation mode.
摘要翻译：一种信息处理装置，包括：处理单元; 外围电路模块; 以及引导地址寄存器，其中所述信息处理设备包括具有低于所述第一操作模式的操作电流的第一操作模式和第二操作模式，其中所述引导地址寄存器保存要执行的指令的地址所述处理单元首先当所述引导地址寄存器从所述第二操作模式返回到所述第一操作模式时，其中当所述信息处理设备从所述第二操作模式转换到所述第一操作时，所述地址从所述引导地址输出到所述处理单元模式。

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