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1. 发明申请

US20050247675A1 Treatment of dies prior to nickel silicide formation 审中-公开
标题翻译：在硅化镍形成之前处理模具
公开(公告)号：US20050247675A1
公开(公告)日：2005-11-10
申请号：US10950979
申请日：2004-09-27
申请人： Mona Eissa , Nilesh Doke , Eden Zielinski , Gregory Shinn
发明人： Mona Eissa , Nilesh Doke , Eden Zielinski , Gregory Shinn
IPC分类号： B44C1/22 , C23F1/00 , C23G1/20 , H01L21/02 , H01L21/321 , H01L21/3213
CPC分类号： H01L21/02074 , C23G1/20
摘要： A post chemical-mechanical polishing cleaning method, comprising contacting a die with a first chemistry that removes at least some organic compounds and ions from a surface of the die. After contacting the die with the first chemistry, the method further comprises contacting the die with a second chemistry that removes at least some copper abutting the die surface. The method further comprises rinsing and drying the die.
摘要翻译：一种后化学机械抛光清洗方法，包括使模具与第一化学物质接触，所述第一化学物质从模具的表面除去至少一些有机化合物和离子。在使模具与第一化学品接触之后，该方法还包括使模具与第二化学物质接触，该第二化学物质移除邻近管芯表面的至少一些铜。该方法还包括冲洗和干燥模具。

2. 发明申请

US20070181532A1 CMP CLEAN PROCESS FOR HIGH PERFORMANCE COPPER/LOW-K DEVICES 审中-公开
标题翻译：用于高性能铜/低K器件的CMP清洁工艺
公开(公告)号：US20070181532A1
公开(公告)日：2007-08-09
申请号：US11734061
申请日：2007-04-11
申请人： Mona EISSA , Nilesh Doke , Eden Zielinski , Gregory Shinn
发明人： Mona EISSA , Nilesh Doke , Eden Zielinski , Gregory Shinn
IPC分类号： B08B3/00 , B44C1/22 , H01L21/302 , H01L21/461
CPC分类号： H01L21/02074 , C23G1/20
摘要： A post chemical-mechanical polishing cleaning method, comprising contacting a die with a first chemistry that removes at least some organic compounds and ions from a surface of the die. After contacting the die with the first chemistry, the method further comprises contacting the die with a second chemistry that removes at least some copper abutting the die surface. The method further comprises rinsing and drying the die.
摘要翻译：一种后化学机械抛光清洗方法，包括使模具与第一化学物质接触，所述第一化学物质从模具的表面除去至少一些有机化合物和离子。在使模具与第一化学品接触之后，该方法还包括使模具与第二化学物质接触，该第二化学物质移除邻近管芯表面的至少一些铜。该方法还包括冲洗和干燥模具。

3. 发明申请

US20060110920A1 Low temperature nitride used as cu barrier layer 有权
公开(公告)号：US20060110920A1
公开(公告)日：2006-05-25
申请号：US11328865
申请日：2006-01-09
申请人： Zhiping Yin , Eden Zielinski , Fred Fishburn
发明人： Zhiping Yin , Eden Zielinski , Fred Fishburn
IPC分类号： H01L21/44 , H01L21/471
CPC分类号： H01L23/53238 , C23C16/345 , H01L21/3185 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of depositing a non-conductive barrier layer onto a metal surface wherein the resistance of the metal remains substantially unchanged before and after the non-conductive barrier layer deposition. The deposition process provides a low temperature processing environment so as to inhibit the formation of impurities such as silicide in the metal, wherein the silicide can adversely increase the resistance of the underlying metal.

4. 发明授权

US07186642B2 Low temperature nitride used as Cu barrier layer 有权
标题翻译：低温氮化物用作Cu阻挡层
公开(公告)号：US07186642B2
公开(公告)日：2007-03-06
申请号：US11328865
申请日：2006-01-09
申请人： Zhiping Yin , Eden Zielinski , Fred Fishburn
发明人： Zhiping Yin , Eden Zielinski , Fred Fishburn
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , C23C16/345 , H01L21/3185 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of depositing a non-conductive barrier layer onto a metal surface wherein the resistance of the metal remains substantially unchanged before and after the non-conductive barrier layer deposition. The deposition process provides a low temperature processing environment so as to inhibit the formation of impurities such as silicide in the metal, wherein the silicide can adversely increase the resistance of the underlying metal.
摘要翻译：在金属表面上沉积非导电阻挡层的方法，其中金属的电阻在非导电阻挡层沉积之前和之后基本保持不变。沉积工艺提供了低温处理环境，以便抑制在金属中形成诸如硅化物的杂质，其中硅化物可以不利地增加下面的金属的电阻。

5. 发明授权

US06984893B2 Low temperature nitride used as Cu barrier layer 有权
公开(公告)号：US06984893B2
公开(公告)日：2006-01-10
申请号：US10303585
申请日：2002-11-22
申请人： Zhiping Yin , Eden Zielinski , Fred Fishburn
发明人： Zhiping Yin , Eden Zielinski , Fred Fishburn
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , C23C16/345 , H01L21/3185 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of depositing a non-conductive barrier layer onto a metal surface wherein the resistance of the metal remains substantially unchanged before and after the non-conductive barrier layer deposition. The deposition process provides a low temperature processing environment so as to inhibit the formation of impurities such as silicide in the metal, wherein the silicide can adversely increase the resistance of the underlying metal.

6. 发明授权

US06492267B1 Low temperature nitride used as Cu barrier layer 有权
标题翻译：低温氮化物用作Cu阻挡层
公开(公告)号：US06492267B1
公开(公告)日：2002-12-10
申请号：US09503105
申请日：2000-02-11
申请人： Zhiping Yin , Eden Zielinski , Fred Fishburn
发明人： Zhiping Yin , Eden Zielinski , Fred Fishburn
IPC分类号： H01L2144
CPC分类号： H01L23/53238 , C23C16/345 , H01L21/3185 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of depositing a non-conductive barrier layer onto a metal surface wherein the resistance of the metal remains substantially unchanged before and after the non-conductive barrier layer deposition. The deposition process provides a low temperature processing environment so as to inhibit the formation of impurities such as silicide in the metal, wherein the silicide can adversely increase the resistance of the underlying metal.
摘要翻译：在金属表面上沉积非导电阻挡层的方法，其中金属的电阻在非导电阻挡层沉积之前和之后基本保持不变。沉积工艺提供了低温处理环境，以便抑制在金属中形成诸如硅化物的杂质，其中硅化物可以不利地增加下面的金属的电阻。

7. 发明授权

US08241927B2 Methods relating to capacitive monitoring of layer characteristics during back end-of the-line processing 有权
标题翻译：关于在线后处理中的层特性的电容监测的方法
公开(公告)号：US08241927B2
公开(公告)日：2012-08-14
申请号：US12579216
申请日：2009-10-14
申请人： Jihong Choi , Yongsik Moon , Roderick Augur , Eden Zielinski
发明人： Jihong Choi , Yongsik Moon , Roderick Augur , Eden Zielinski
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： Methods are provided that relate to the capacitive monitoring of characteristic pertaining to layer formed during the back end-of-the-line (BEOL) processing of a semiconductor device. In one embodiment, a method includes the steps of forming a first capacitor array including first and second overlying contacts each formed in a different one of the plurality of BEOL layers, measuring the interlayer capacitance between the first and second overlying contacts, and converting the measured interlayer capacitance to a distance between the first and second overlying contacts.
摘要翻译：提供了涉及在半导体器件的后端（BEOL）处理期间形成的层的特性的电容性监测的方法。在一个实施例中，一种方法包括以下步骤：形成第一电容器阵列，该第一电容器阵列包括第一和第二上覆触点，每个形成在多个BEOL层中的不同的一个中，测量第一和第二覆盖触点之间的层间电容，层间电容与第一和第二上覆触点之间的距离。

8. 发明授权

US07214609B2 Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities 有权
标题翻译：用于形成单镶嵌通孔或沟槽的方法以及通过空腔形成双镶嵌
公开(公告)号：US07214609B2
公开(公告)日：2007-05-08
申请号：US10313491
申请日：2002-12-05
申请人： Ping Jiang , Rob Kraft , Guoqiang Xing , Karen H. R. Kirmse , Eden Zielinski
发明人： Ping Jiang , Rob Kraft , Guoqiang Xing , Karen H. R. Kirmse , Eden Zielinski
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76802
摘要： Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching a dielectric layer to form a cavity there and to expose an underlying etch-stop layer, and etching the exposed etch-stop layer to extend the cavity and to expose a conductive feature in an existing interconnect structure, wherein etching the portion of the dielectric layer and etching the exposed portion of the etch-stop layer are performed concurrently with substantially no intervening processing steps therebetween. Also disclosed are methods of forming a via cavity in a dual damascene interconnect structure, comprising forming an etch-stop layer over an existing interconnect structure, forming a dielectric layer over the etch-stop layer, etching a portion of the dielectric layer to form a via cavity in the dielectric layer and to expose a portion of the etch-stop layer, and etching the etch-stop layer to extend the via cavity, where the dielectric layer is covered during etching of the etch-stop layer.
摘要翻译：公开了用于在单个镶嵌互连结构中形成沟槽或通孔腔的方法，包括蚀刻介电层以在其中形成空腔并暴露下面的蚀刻停止层，以及蚀刻暴露的蚀刻停止层以延伸空腔，并且暴露现有互连结构中的导电特征，其中蚀刻介电层的一部分并蚀刻蚀刻停止层的暴露部分同时进行，其间基本上没有中间处理步骤。还公开了在双镶嵌互连结构中形成通孔腔的方法，包括在现有互连结构上形成蚀刻停止层，在蚀刻停止层上形成电介质层，蚀刻介电层的一部分以形成并且暴露蚀刻停止层的一部分，以及蚀刻蚀刻停止层以延伸通孔腔，其中介电层在蚀刻停止层的蚀刻期间被覆盖。

9. 发明授权

US06358849B1 Integrated circuit interconnect and method 有权
标题翻译：集成电路互连和方法
公开(公告)号：US06358849B1
公开(公告)日：2002-03-19
申请号：US09467680
申请日：1999-12-21
申请人： Robert H. Havemann , Girish A. Dixit , Manoj Jain , Eden Zielinski , Qi-Zhong Hong , Jeffrey West
发明人： Robert H. Havemann , Girish A. Dixit , Manoj Jain , Eden Zielinski , Qi-Zhong Hong , Jeffrey West
IPC分类号： H01L21302
CPC分类号： H01L21/76808 , H01L21/31053 , H01L21/76224 , H01L21/76849 , H01L21/76856 , H01L21/76867
摘要： A dual inlaid interconnect fabrication method using a temporary filler in a via during trench etch and removal of the filler after trench etch. This provides via bottom protection during trench etch.
摘要翻译：一种双嵌入互连制造方法，在沟槽蚀刻中沟槽蚀刻和去除填充物之后，在通孔中使用临时填料。这在沟槽蚀刻期间通过底部保护提供。

10. 发明申请

US20110086445A1 METHODS RELATING TO CAPACITIVE MONITORING OF LAYER CHARACTERISTICS DURING BACK END-OF-THE-LINE PROCESSING 有权
标题翻译：在回程末端处理中与层状特性的电容监测有关的方法
公开(公告)号：US20110086445A1
公开(公告)日：2011-04-14
申请号：US12579216
申请日：2009-10-14
申请人： Jihong Choi , Yongsik Moon , Roderick Augur , Eden Zielinski
发明人： Jihong Choi , Yongsik Moon , Roderick Augur , Eden Zielinski
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： Methods are provided that relate to the capacitive monitoring of characteristic pertaining to layer formed during the back end-of-the-line (BEOL) processing of a semiconductor device. In one embodiment, a method includes the steps of forming a first capacitor array including first and second overlying contacts each formed in a different one of the plurality of BEOL layers, measuring the interlayer capacitance between the first and second overlying contacts, and converting the measured interlayer capacitance to a distance between the first and second overlying contacts.
摘要翻译：提供了涉及在半导体器件的后端（BEOL）处理期间形成的层的特性的电容性监测的方法。在一个实施例中，一种方法包括以下步骤：形成第一电容器阵列，该第一电容器阵列包括第一和第二上覆触点，每个形成在多个BEOL层中的不同的一个中，测量第一和第二覆盖触点之间的层间电容，层间电容与第一和第二上覆触点之间的距离。

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