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1. 发明授权

US08572004B2 Space solution search 失效
标题翻译：空间解决方案搜索
公开(公告)号：US08572004B2
公开(公告)日：2013-10-29
申请号：US12649064
申请日：2009-12-29
申请人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Navraj Singh
发明人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Navraj Singh
IPC分类号： G06E1/00 , G06E3/00 , G06F15/00 , G06G7/00 , G06N99/00
CPC分类号： G06N3/126 , G06F17/5009 , G06F2217/10
摘要： A statistical approach can be used to efficiently supply an initial population that provides a good global description of a design space. The SI based simulation can then find a global best design within a reduced number of simulations. The statistical approach can be utilized to determine a plurality of potential best and worst case designs from a design space. The plurality of potential best and worst case designs from the design space seed or prime a SI based simulation. The best case designs are based on design parameters than can be controlled. The worst case designs are based on design parameters than cannot be controlled due. SI based simulations can then be run on the best case designs with respect to the worst case designs to determine probability of failure of the best case design.
摘要翻译：可以使用统计方法来有效地提供提供设计空间的良好全局描述的初始种群。然后，基于SI的仿真可以在减少数量的模拟中找到全局最佳设计。统计方法可用于从设计空间确定多个潜在的最佳和最差情况设计。从设计空间种子的多个潜在的最佳和最坏情况的设计或基于SI的模拟。最好的案例设计是基于设计参数而不是可控制的。最坏的情况设计是基于设计参数而不是不能控制的。然后可以在最坏情况设计的最佳案例设计上运行基于SI的模拟，以确定最佳案例设计的故障概率。

2. 发明申请

US20110161055A1 SPACE SOLUTION SEARCH 失效
标题翻译：空间解决方案搜索
公开(公告)号：US20110161055A1
公开(公告)日：2011-06-30
申请号：US12649064
申请日：2009-12-29
申请人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Navraj Singh
发明人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Navraj Singh
IPC分类号： G06F17/50 , G06N3/12 , G06G7/62
CPC分类号： G06N3/126 , G06F17/5009 , G06F2217/10
摘要： A statistical approach can be used to efficiently supply an initial population that provides a good global description of a design space. The SI based simulation can then find a global best design within a reduced number of simulations. The statistical approach can be utilized to determine a plurality of potential best and worst case designs from a design space. The plurality of potential best and worst case designs from the design space seed or prime a SI based simulation. The best case designs are based on design parameters than can be controlled. The worst case designs are based on design parameters than cannot be controlled due. SI based simulations can then be run on the best case designs with respect to the worst case designs to determine probability of failure of the best case design.
摘要翻译：可以使用统计方法来有效地提供提供设计空间的良好全局描述的初始种群。然后，基于SI的仿真可以在减少数量的模拟中找到全局最佳设计。统计方法可用于从设计空间确定多个潜在的最佳和最差情况设计。从设计空间种子的多个潜在的最佳和最坏情况的设计或基于SI的模拟。最好的案例设计是基于设计参数而不是可控制的。最坏的情况设计是基于设计参数而不是不能控制的。然后可以在最坏情况设计的最佳案例设计上运行基于SI的模拟，以确定最佳案例设计的故障概率。

3. 发明申请

US20100014569A1 Identifying An Optimized Test Bit Pattern For Analyzing Electrical Communications Channel Topologies 失效
标题翻译：识别用于分析电气通信通道拓扑的优化测试位模式
公开(公告)号：US20100014569A1
公开(公告)日：2010-01-21
申请号：US12174349
申请日：2008-07-16
申请人： Moises Cases , Bhyrav M. Mutnury , Navraj Singh , Caleb J. Wesley
发明人： Moises Cases , Bhyrav M. Mutnury , Navraj Singh , Caleb J. Wesley
IPC分类号： H04B17/00
CPC分类号： H04L43/50
摘要： Identifying an optimized test bit pattern for analyzing electrical communications channel topologies, including: ranking according to channel quality, from worst to best, a set of channel topologies for an electrical communications channel; and for each ranked channel topology beginning with the worst, carrying out the following steps in an iterative loop until a concatenated test bit pattern and a previously optimized test bit pattern are functionally equally fit: concatenating to a previously optimized test bit pattern an additional test bit pattern; optimizing the concatenated test bit pattern values for a next ranked channel in the subset, leaving the optimized values of the previously optimized test bit pattern unchanged; and comparing through use of a fitness function the relative qualities of the previously optimized test bit pattern and the optimized concatenated test bit pattern.
摘要翻译：识别用于分析电气通信信道拓扑的优化的测试位模式，包括：根据信道质量进行排序，从最差到最佳，用于电通信信道的一组信道拓扑; 并且对于以最坏情况开始的每个排名的信道拓扑，在迭代循环中执行以下步骤，直到级联的测试位模式和先前优化的测试位模式在功能上是相等的：连接到先前优化的测试位模式，附加测试位模式; 优化子集中下一个排名的信道的级联测试位模式值，保留先前优化的测试位模式的优化值不变; 并且通过使用适应度函数来比较先前优化的测试位模式和优化的级联测试位模式的相对质量。

4. 发明授权

US08327196B2 Identifying an optimized test bit pattern for analyzing electrical communications channel topologies 失效
标题翻译：识别用于分析电气通信信道拓扑的优化测试位模式
公开(公告)号：US08327196B2
公开(公告)日：2012-12-04
申请号：US12174349
申请日：2008-07-16
申请人： Moises Cases , Bhyrav M. Mutnury , Navraj Singh , Caleb J. Wesley
发明人： Moises Cases , Bhyrav M. Mutnury , Navraj Singh , Caleb J. Wesley
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： H04L43/50
摘要： Identifying an optimized test bit pattern for analyzing electrical communications channel topologies, including: ranking according to channel quality, from worst to best, a set of channel topologies for an electrical communications channel; and for each ranked channel topology beginning with the worst, carrying out the following steps in an iterative loop until a concatenated test bit pattern and a previously optimized test bit pattern are functionally equally fit: concatenating to a previously optimized test bit pattern an additional test bit pattern; optimizing the concatenated test bit pattern values for a next ranked channel in the subset, leaving the optimized values of the previously optimized test bit pattern unchanged; and comparing through use of a fitness function the relative qualities of the previously optimized test bit pattern and the optimized concatenated test bit pattern.
摘要翻译：识别用于分析电气通信信道拓扑的优化的测试位模式，包括：根据信道质量进行排序，从最差到最佳，用于电通信信道的一组信道拓扑; 并且对于以最坏情况开始的每个排名的信道拓扑，在迭代循环中执行以下步骤，直到级联的测试位模式和先前优化的测试位模式在功能上相等地适合：级联到先前优化的测试位模式，附加测试位模式; 优化子集中下一个排名的信道的级联测试位模式值，保留先前优化的测试位模式的优化值不变; 并且通过使用适应度函数来比较先前优化的测试位模式和优化的级联测试位模式的相对质量。

5. 发明授权

US08453081B2 Electrical design space exploration 失效
标题翻译：电气设计空间探索
公开(公告)号：US08453081B2
公开(公告)日：2013-05-28
申请号：US12784150
申请日：2010-05-20
申请人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Caleb J. Wesley
发明人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Caleb J. Wesley
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F2217/08
摘要： A method for electrical design space exploration includes receiving a template for an electrical design. Design component parameters associated with at least one component in the electrical design are also received. Weighted factors are assigned to design complexity parameters of the electrical design. The parameters of the complexity can include at least one of following: whether the electrical design is known, a number of the design component parameters, a level of interaction among the design component parameters, a time constraint and a memory restriction of a simulation, and whether a statistical analysis or a worst case approach is used to analyze an output of the simulation. A simulation approach for design space exploration of the electrical design is selected based on the weighted factors for the parameters of the complexity of the electrical design. The simulation is performed based on the selected simulation approach.
摘要翻译：电气设计空间探索的方法包括接收电气设计的模板。还接收与电气设计中的至少一个组件相关联的设计组件参数。加权因子分配给电气设计的设计复杂性参数。复杂性的参数可以包括以下至少一个：电气设计是否已知，多个设计组件参数，设计组件参数之间的交互级别，时间约束和模拟的存储器限制，以及是否使用统计分析或最坏情况的方法来分析模拟的输出。基于电气设计复杂度参数的加权因子，选择电气设计空间探索的仿真方法。基于选择的模拟方法进行模拟。

6. 发明申请

US20110289463A1 ELECTRICAL DESIGN SPACE EXPLORATION 失效
标题翻译：电气设计空间探索
公开(公告)号：US20110289463A1
公开(公告)日：2011-11-24
申请号：US12784150
申请日：2010-05-20
申请人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Caleb J. Wesley
发明人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Caleb J. Wesley
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F2217/08
摘要： A method for electrical design space exploration includes receiving a template for an electrical design. Design component parameters associated with at least one component in the electrical design are also received. Weighted factors are assigned to design complexity parameters of the electrical design. The parameters of the complexity can include at least one of following: whether the electrical design is known, a number of the design component parameters, a level of interaction among the design component parameters, a time constraint and a memory restriction of a simulation, and whether a statistical analysis or a worst case approach is used to analyze an output of the simulation. A simulation approach for design space exploration of the electrical design is selected based on the weighted factors for the parameters of the complexity of the electrical design. The simulation is performed based on the selected simulation approach.
摘要翻译：电气设计空间探索的方法包括接收电气设计的模板。还接收与电气设计中的至少一个组件相关联的设计组件参数。加权因子分配给电气设计的设计复杂性参数。复杂性的参数可以包括以下至少一个：电气设计是否已知，多个设计组件参数，设计组件参数之间的交互级别，时间约束和模拟的存储器限制，以及是否使用统计分析或最坏情况的方法来分析模拟的输出。基于电气设计复杂度参数的加权因子，选择电气设计空间探索的仿真方法。基于选择的模拟方法进行模拟。

7. 发明申请

US20090307636A1 SOLUTION EFFICIENCY OF GENETIC ALGORITHM APPLICATIONS 审中-公开
标题翻译：遗传算法应用的解决方案效率
公开(公告)号：US20090307636A1
公开(公告)日：2009-12-10
申请号：US12133480
申请日：2008-06-05
申请人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Caleb J. Wesley
发明人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Caleb J. Wesley
IPC分类号： G06F17/50 , G06N3/12
CPC分类号： G06F17/505 , G06F2217/08 , G06N3/126
摘要： A method of optimizing a very large scale integrated circuit design takes a circuit description which includes interconnected circuit components and characteristic variables assigned to the circuit components such as environmental, operational or process parameters, computes a first solution for the characteristic variables using a statistical analysis, and then computes a second solution for the characteristic variables using an evolutionary analysis seeded by the first solution. In the exemplary implementation the statistical analysis is a central composite design (CCD) and the evolutionary analysis is a genetic algorithm. Best case and worst case CCD solutions may be used to seed separate genetic algorithm runs and derive global best case and global worst case solutions. These solutions may be compared for sensitivity analysis. The method thereby provides significant reduction in time-to-solution with accurate simulation results.
摘要翻译：优化大规模集成电路设计的方法采用包括互连电路组件和分配给诸如环境，操作或过程参数的电路组件的特征变量的电路描述，使用统计分析来计算特征变量的第一解，然后使用第一个解决方案种子进化的分析计算特征变量的第二个解决方案。在示例性实施中，统计分析是中心复合设计（CCD），进化分析是遗传算法。最佳情况和最坏情况CCD解决方案可用于种子分离遗传算法运行，并得出全球最佳情况和全球最坏情况解决方案。可以将这些解决方案进行灵敏度分析。因此，该方法通过精确的模拟结果显着减少了解决方案的时间。

8. 发明申请

US20100294557A1 Transmission Cable with Spirally Wrapped Shielding 有权
标题翻译：带螺旋缠绕屏蔽的传输电缆
公开(公告)号：US20100294557A1
公开(公告)日：2010-11-25
申请号：US12468327
申请日：2009-05-19
申请人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury
发明人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury
IPC分类号： H05K9/00
CPC分类号： H01B11/203 , H01B7/0823 , H01B11/1025 , H01B11/1091
摘要： Embodiments of the invention are directed to transmission cables, and particularly to twinax cables, for transmitting digital data and other information between components in a data processing environment. One embodiment of the invention is directed to an information transmission cable that comprises first and second signal carrying conductors of specified length, each of the signal carrying conductors being disposed to carry information signals and having a longitudinal axis. The embodiment further includes an insulating structure comprising an amount of specified dielectric insulation material, the insulating structure being positioned to surround the first and second signal carrying conductors along their respective lengths, and acting to maintain the first and second signal conductors in spaced apart parallel relationship with each other. A first drain conductor is positioned proximate to the first signal carrying conductor in spaced apart parallel relationship, and is further positioned in a first prespecified relationship with a reference line that intersects the respective longitudinal axes of the first and second signal carrying conductors, and that lies in a plane orthogonal thereto. In similar manner, a second drain conductor is positioned proximate to the second signal carrying conductor in spaced apart parallel relationship, and is further positioned in a second prespecified relationship with the reference line. Shielding material is spirally wrapped around the first and second signaling conductors, the first and second drain conductors and the insulating structure.
摘要翻译：本发明的实施例涉及用于在数据处理环境中在组件之间传送数字数据和其他信息的传输电缆，特别是双芯电缆。本发明的一个实施例涉及一种信息传输电缆，其包括具有指定长度的第一和第二信号承载导体，每个信号承载导体设置为承载信息信号并具有纵向轴线。该实施例还包括绝缘结构，该绝缘结构包括一定量的介电绝缘材料，该绝缘结构被定位成沿其相应的长度包围第一和第二信号承载导体，并且用于将第一和第二信号导体保持间隔开的平行关系与彼此。第一漏极导体以间隔开的平行关系定位成靠近第一信号承载导体，并且进一步定位成与与第一和第二信号承载导体的相应纵轴相交的参考线的第一预定关系，并且位于在与其正交的平面内。以类似的方式，第二漏极导体以间隔开的平行关系定位成靠近第二信号承载导体，并且还以与参考线的第二预定关系进一步定位。屏蔽材料螺旋缠绕在第一和第二信号导体，第一和第二漏极导体和绝缘结构周围。

9. 发明申请

US20100229131A1 SWARM INTELLIGENCE FOR ELECTRICAL DESIGN SPACE MODELING AND OPTIMIZATION 有权
标题翻译：电气设计空间建模与优化的SWARM智能
公开(公告)号：US20100229131A1
公开(公告)日：2010-09-09
申请号：US12398535
申请日：2009-03-05
申请人： Moises Cases , Jinwoo Choi , Bhyrav Mutnury , Navraj Singh , Caleb J. Wesley
发明人： Moises Cases , Jinwoo Choi , Bhyrav Mutnury , Navraj Singh , Caleb J. Wesley
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/08
摘要： A method, system, and computer program product for exploring and optimizing an electrical design space. A computer receiving a design space assigns a plurality of initial values (random or predetermined) for optimizing the design space. A particle swarm containing a plurality of particles is created and an optimization of the design space is then performed using the assigned initial values. Following completion of optimization, the global best and personal best for each particle are updated. Velocity vectors and position vectors of the design space are then updated before the computer performs the optimization process again. The process loops, continually updating global and personal bests and velocity and position vectors until a termination criteria is reached. Upon reaching the termination criteria, the best fitness of each particle of the swarm is assigned as an optimized design space. In an alternate embodiment, the particle with the worst target fitness may be assigned.
摘要翻译：一种用于探索和优化电气设计空间的方法，系统和计算机程序产品。接收设计空间的计算机分配用于优化设计空间的多个初始值（随机或预定）。产生包含多个粒子的粒子群，然后使用分配的初始值来执行设计空间的优化。在优化完成后，更新每个粒子的全球最佳和个人最好的。然后在计算机再次执行优化处理之前更新设计空间的速度向量和位置向量。过程循环，持续更新全局和个人最佳状态以及速度和位置向量，直到达到终止标准。达到终止标准后，群体的每个粒子的最佳适应度被指定为优化的设计空间。在替代实施例中，可以分配具有最差目标适应度的粒子。

10. 发明授权

US08276106B2 Swarm intelligence for electrical design space modeling and optimization 有权
标题翻译：用于电气设计空间建模和优化的群体智能
公开(公告)号：US08276106B2
公开(公告)日：2012-09-25
申请号：US12398535
申请日：2009-03-05
申请人： Moises Cases , Jinwoo Choi , Bhyrav Mutnury , Navraj Singh , Caleb J. Wesley
发明人： Moises Cases , Jinwoo Choi , Bhyrav Mutnury , Navraj Singh , Caleb J. Wesley
IPC分类号： G06F17/50 , G06G7/48
CPC分类号： G06F17/5045 , G06F2217/08
摘要： A method, system, and computer program product for exploring and optimizing an electrical design space. A computer receiving a design space assigns a plurality of initial values (random or predetermined) for optimizing the design space. A particle swarm containing a plurality of particles is created and an optimization of the design space is then performed using the assigned initial values. Following completion of optimization, the global best and personal best for each particle are updated. Velocity vectors and position vectors of the design space are then updated before the computer performs the optimization process again. The process loops, continually updating global and personal bests and velocity and position vectors until a termination criteria is reached. Upon reaching the termination criteria, the best fitness of each particle of the swarm is assigned as an optimized design space. In an alternate embodiment, the particle with the worst target fitness may be assigned.
摘要翻译：一种用于探索和优化电气设计空间的方法，系统和计算机程序产品。接收设计空间的计算机分配用于优化设计空间的多个初始值（随机或预定）。产生包含多个粒子的粒子群，然后使用分配的初始值来执行设计空间的优化。在优化完成后，更新每个粒子的全球最佳和个人最好的。然后在计算机再次执行优化处理之前更新设计空间的速度向量和位置向量。过程循环，持续更新全局和个人最佳状态以及速度和位置向量，直到达到终止标准。达到终止标准后，群体的每个粒子的最佳适应度被指定为优化的设计空间。在替代实施例中，可以分配具有最差目标适应度的粒子。

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