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1. 发明申请

US20100014569A1 Identifying An Optimized Test Bit Pattern For Analyzing Electrical Communications Channel Topologies 失效
标题翻译：识别用于分析电气通信通道拓扑的优化测试位模式
公开(公告)号：US20100014569A1
公开(公告)日：2010-01-21
申请号：US12174349
申请日：2008-07-16
申请人： Moises Cases , Bhyrav M. Mutnury , Navraj Singh , Caleb J. Wesley
发明人： Moises Cases , Bhyrav M. Mutnury , Navraj Singh , Caleb J. Wesley
IPC分类号： H04B17/00
CPC分类号： H04L43/50
摘要： Identifying an optimized test bit pattern for analyzing electrical communications channel topologies, including: ranking according to channel quality, from worst to best, a set of channel topologies for an electrical communications channel; and for each ranked channel topology beginning with the worst, carrying out the following steps in an iterative loop until a concatenated test bit pattern and a previously optimized test bit pattern are functionally equally fit: concatenating to a previously optimized test bit pattern an additional test bit pattern; optimizing the concatenated test bit pattern values for a next ranked channel in the subset, leaving the optimized values of the previously optimized test bit pattern unchanged; and comparing through use of a fitness function the relative qualities of the previously optimized test bit pattern and the optimized concatenated test bit pattern.
摘要翻译：识别用于分析电气通信信道拓扑的优化的测试位模式，包括：根据信道质量进行排序，从最差到最佳，用于电通信信道的一组信道拓扑; 并且对于以最坏情况开始的每个排名的信道拓扑，在迭代循环中执行以下步骤，直到级联的测试位模式和先前优化的测试位模式在功能上是相等的：连接到先前优化的测试位模式，附加测试位模式; 优化子集中下一个排名的信道的级联测试位模式值，保留先前优化的测试位模式的优化值不变; 并且通过使用适应度函数来比较先前优化的测试位模式和优化的级联测试位模式的相对质量。

2. 发明授权

US08327196B2 Identifying an optimized test bit pattern for analyzing electrical communications channel topologies 失效
标题翻译：识别用于分析电气通信信道拓扑的优化测试位模式
公开(公告)号：US08327196B2
公开(公告)日：2012-12-04
申请号：US12174349
申请日：2008-07-16
申请人： Moises Cases , Bhyrav M. Mutnury , Navraj Singh , Caleb J. Wesley
发明人： Moises Cases , Bhyrav M. Mutnury , Navraj Singh , Caleb J. Wesley
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： H04L43/50
摘要： Identifying an optimized test bit pattern for analyzing electrical communications channel topologies, including: ranking according to channel quality, from worst to best, a set of channel topologies for an electrical communications channel; and for each ranked channel topology beginning with the worst, carrying out the following steps in an iterative loop until a concatenated test bit pattern and a previously optimized test bit pattern are functionally equally fit: concatenating to a previously optimized test bit pattern an additional test bit pattern; optimizing the concatenated test bit pattern values for a next ranked channel in the subset, leaving the optimized values of the previously optimized test bit pattern unchanged; and comparing through use of a fitness function the relative qualities of the previously optimized test bit pattern and the optimized concatenated test bit pattern.
摘要翻译：识别用于分析电气通信信道拓扑的优化的测试位模式，包括：根据信道质量进行排序，从最差到最佳，用于电通信信道的一组信道拓扑; 并且对于以最坏情况开始的每个排名的信道拓扑，在迭代循环中执行以下步骤，直到级联的测试位模式和先前优化的测试位模式在功能上相等地适合：级联到先前优化的测试位模式，附加测试位模式; 优化子集中下一个排名的信道的级联测试位模式值，保留先前优化的测试位模式的优化值不变; 并且通过使用适应度函数来比较先前优化的测试位模式和优化的级联测试位模式的相对质量。

3. 发明授权

US08453081B2 Electrical design space exploration 失效
标题翻译：电气设计空间探索
公开(公告)号：US08453081B2
公开(公告)日：2013-05-28
申请号：US12784150
申请日：2010-05-20
申请人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Caleb J. Wesley
发明人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Caleb J. Wesley
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F2217/08
摘要： A method for electrical design space exploration includes receiving a template for an electrical design. Design component parameters associated with at least one component in the electrical design are also received. Weighted factors are assigned to design complexity parameters of the electrical design. The parameters of the complexity can include at least one of following: whether the electrical design is known, a number of the design component parameters, a level of interaction among the design component parameters, a time constraint and a memory restriction of a simulation, and whether a statistical analysis or a worst case approach is used to analyze an output of the simulation. A simulation approach for design space exploration of the electrical design is selected based on the weighted factors for the parameters of the complexity of the electrical design. The simulation is performed based on the selected simulation approach.
摘要翻译：电气设计空间探索的方法包括接收电气设计的模板。还接收与电气设计中的至少一个组件相关联的设计组件参数。加权因子分配给电气设计的设计复杂性参数。复杂性的参数可以包括以下至少一个：电气设计是否已知，多个设计组件参数，设计组件参数之间的交互级别，时间约束和模拟的存储器限制，以及是否使用统计分析或最坏情况的方法来分析模拟的输出。基于电气设计复杂度参数的加权因子，选择电气设计空间探索的仿真方法。基于选择的模拟方法进行模拟。

4. 发明授权

US07533458B1 Method for reducing noise coupling in high speed digital systems 失效
标题翻译：降低高速数字系统噪声耦合的方法
公开(公告)号：US07533458B1
公开(公告)日：2009-05-19
申请号：US12174810
申请日：2008-07-17
申请人： Moises Cases , Bradley D. Herrman , Kent B. Howieson , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham , Caleb J. Wesley
发明人： Moises Cases , Bradley D. Herrman , Kent B. Howieson , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham , Caleb J. Wesley
IPC分类号： H05K3/36
CPC分类号： H05K1/024 , H05K3/4611 , H05K3/4697 , H05K2201/09236 , H05K2201/09318 , H05K2203/063 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T156/1013
摘要： Methods and systems for reducing noise coupling in high-speed digital systems. Exemplary embodiments include a method, including etching a plurality of high speed signal traces onto a core insulating layer, forming trenches on respective sides of the plurality of high speed signal traces, thereby removing insulating material adjacent to the plurality of high speed signal traces and forming pedestals having remaining insulating material, the plurality of high speed signal traces disposed on and coupled to the remaining insulating material, coupling pre-preg material on the high speed signal traces, removing the pre-preg material adjacent the trenches, thereby retaining the pre-preg material aligned with the high speed signal traces, and heating and pressing a core layer to the pre-preg layer, and heating and pressing the pre-preg layer to the core insulating layer.
摘要翻译：降低高速数字系统噪声耦合的方法和系统。示例性实施例包括一种方法，包括将多个高速信号迹线蚀刻到芯绝缘层上，在多个高速信号迹线的相应侧上形成沟槽，从而去除与多个高速信号迹线相邻的绝缘材料，并形成具有剩余绝缘材料的基座，多个高速信号迹线设置在剩余绝缘材料上并耦合到剩余的绝缘材料上，将高速信号迹线上的预预处理材料耦合，去除与沟槽相邻的预浸料，将材料与高速信号迹线对准，并且将芯层加热并压制到预浸层，以及将预浸层加热和压制到芯绝缘层。

5. 发明申请

US20110289463A1 ELECTRICAL DESIGN SPACE EXPLORATION 失效
标题翻译：电气设计空间探索
公开(公告)号：US20110289463A1
公开(公告)日：2011-11-24
申请号：US12784150
申请日：2010-05-20
申请人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Caleb J. Wesley
发明人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Caleb J. Wesley
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F2217/08
摘要： A method for electrical design space exploration includes receiving a template for an electrical design. Design component parameters associated with at least one component in the electrical design are also received. Weighted factors are assigned to design complexity parameters of the electrical design. The parameters of the complexity can include at least one of following: whether the electrical design is known, a number of the design component parameters, a level of interaction among the design component parameters, a time constraint and a memory restriction of a simulation, and whether a statistical analysis or a worst case approach is used to analyze an output of the simulation. A simulation approach for design space exploration of the electrical design is selected based on the weighted factors for the parameters of the complexity of the electrical design. The simulation is performed based on the selected simulation approach.
摘要翻译：电气设计空间探索的方法包括接收电气设计的模板。还接收与电气设计中的至少一个组件相关联的设计组件参数。加权因子分配给电气设计的设计复杂性参数。复杂性的参数可以包括以下至少一个：电气设计是否已知，多个设计组件参数，设计组件参数之间的交互级别，时间约束和模拟的存储器限制，以及是否使用统计分析或最坏情况的方法来分析模拟的输出。基于电气设计复杂度参数的加权因子，选择电气设计空间探索的仿真方法。基于选择的模拟方法进行模拟。

6. 发明申请

US20090107705A1 METHODS AND SYSTEMS FOR REDUCING NOISE COUPLING IN HIGH SPEED DIGITAL SYSTEMS 有权
标题翻译：用于降低高速数字系统噪声耦合的方法和系统
公开(公告)号：US20090107705A1
公开(公告)日：2009-04-30
申请号：US11924416
申请日：2007-10-25
申请人： Moises Cases , Bradley D. Herrman , Kent B. Howieson , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham , Caleb J. Wesley
发明人： Moises Cases , Bradley D. Herrman , Kent B. Howieson , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham , Caleb J. Wesley
IPC分类号： H05K3/00 , H05K1/03
CPC分类号： H05K1/024 , H05K3/4611 , H05K3/4697 , H05K2201/09236 , H05K2201/09318 , H05K2203/063 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T156/1013
摘要： Methods and systems for reducing noise coupling in high-speed digital systems. Exemplary embodiments include a method, including etching a plurality of high speed signal traces onto a core insulating layer, forming trenches on respective sides of the plurality of high speed signal traces, thereby removing insulating material adjacent to the plurality of high speed signal traces and forming pedestals having remaining insulating material, the plurality of high speed signal traces disposed on and coupled to the remaining insulating material, coupling pre-preg material on the high speed signal traces, removing the pre-preg material adjacent the trenches, thereby retaining the pre-preg material aligned with the high speed signal traces, and heating and pressing a core layer to the pre-preg layer, and heating and pressing the pre-preg layer to the core insulating layer.
摘要翻译：降低高速数字系统噪声耦合的方法和系统。示例性实施例包括一种方法，包括将多个高速信号迹线蚀刻到芯绝缘层上，在多个高速信号迹线的相应侧上形成沟槽，从而去除与多个高速信号迹线相邻的绝缘材料，并形成具有剩余绝缘材料的基座，多个高速信号迹线设置在剩余绝缘材料上并耦合到剩余的绝缘材料上，将高速信号迹线上的预预处理材料耦合，去除与沟槽相邻的预浸料，将材料与高速信号迹线对准，并且将芯层加热并压制到预浸层，以及将预浸层加热和压制到芯绝缘层。

7. 发明申请

US20090106976A1 METHOD FOR REDUCING NOISE COUPLING IN HIGH SPEED DIGITAL SYSTEMS 失效
标题翻译：降低高速数字系统噪声耦合的方法
公开(公告)号：US20090106976A1
公开(公告)日：2009-04-30
申请号：US12174810
申请日：2008-07-17
申请人： Moises Cases , Bradley D. Herrman , Kent B. Howieson , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham , Caleb J. Wesley
发明人： Moises Cases , Bradley D. Herrman , Kent B. Howieson , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham , Caleb J. Wesley
IPC分类号： H05K3/02 , B29C53/00
CPC分类号： H05K1/024 , H05K3/4611 , H05K3/4697 , H05K2201/09236 , H05K2201/09318 , H05K2203/063 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T156/1013
摘要： Methods and systems for reducing noise coupling in high-speed digital systems. Exemplary embodiments include a method, including etching a plurality of high speed signal traces onto a core insulating layer, forming trenches on respective sides of the plurality of high speed signal traces, thereby removing insulating material adjacent to the plurality of high speed signal traces and forming pedestals having remaining insulating material, the plurality of high speed signal traces disposed on and coupled to the remaining insulating material, coupling pre-preg material on the high speed signal traces, removing the pre-preg material adjacent the trenches, thereby retaining the pre-preg material aligned with the high speed signal traces, and heating and pressing a core layer to the pre-preg layer, and heating and pressing the pre-preg layer to the core insulating layer.
摘要翻译：降低高速数字系统噪声耦合的方法和系统。示例性实施例包括一种方法，包括将多个高速信号迹线蚀刻到芯绝缘层上，在多个高速信号迹线的相应侧上形成沟槽，从而去除与多个高速信号迹线相邻的绝缘材料，并形成具有剩余绝缘材料的基座，多个高速信号迹线设置在剩余绝缘材料上并耦合到剩余的绝缘材料上，将高速信号迹线上的预预处理材料耦合，去除与沟槽相邻的预浸料，将材料与高速信号迹线对准，并且将芯层加热并压制到预浸层，以及将预浸层加热和压制到芯绝缘层。

8. 发明授权

US08084692B2 Reducing noise coupling in high speed digital systems 有权
标题翻译：降低高速数字系统中的噪声耦合
公开(公告)号：US08084692B2
公开(公告)日：2011-12-27
申请号：US11924416
申请日：2007-10-25
申请人： Moises Cases , Bradley D. Herrman , Kent B. Howieson , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham , Caleb J. Wesley
发明人： Moises Cases , Bradley D. Herrman , Kent B. Howieson , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham , Caleb J. Wesley
IPC分类号： H05K1/03
CPC分类号： H05K1/024 , H05K3/4611 , H05K3/4697 , H05K2201/09236 , H05K2201/09318 , H05K2203/063 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T156/1013
摘要： An apparatus having reduced noise coupling includes a core layer having an upper and lower surface, the upper and lower surface each including a copper sheet layer, a pre-preg layer having an upper surface and a lower surface, the upper surface of the pre-preg layer coupled to the lower surface of the core layer, a core insulating layer having an upper surface and a lower surface, the upper surface of the core insulating layer coupled to the lower surface of the pre-preg layer, a return current reference layer disposed on the lower surface of the core insulator layer and high-speed signal traces disposed on the upper surface of the core insulating layer, each of the high speed signal traces disposed on a pedestal defined by a section of the pre-preg layer and the core insulating layer, each pedestal being separated by an air gap disposed between adjacent pedestals.
摘要翻译：具有降低的噪声耦合的装置包括具有上表面和下表面的芯层，所述上表面和下表面各自包括铜片层，具有上表面和下表面的预浸层，耦合到芯层的下表面的芯层绝缘层，具有上表面和下表面的芯绝缘层，芯绝缘层的上表面耦合到预浸层的下表面，返回电流参考层设置在芯绝缘体层的下表面和设置在芯绝缘层的上表面上的高速信号迹线，每个高速信号迹线设置在由预浸层的一部分限定的基座上，芯绝缘层，每个基座由设置在相邻基座之间的气隙分隔开。

9. 发明申请

US20090307636A1 SOLUTION EFFICIENCY OF GENETIC ALGORITHM APPLICATIONS 审中-公开
标题翻译：遗传算法应用的解决方案效率
公开(公告)号：US20090307636A1
公开(公告)日：2009-12-10
申请号：US12133480
申请日：2008-06-05
申请人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Caleb J. Wesley
发明人： Moises Cases , Jinwoo Choi , Bhyrav M. Mutnury , Caleb J. Wesley
IPC分类号： G06F17/50 , G06N3/12
CPC分类号： G06F17/505 , G06F2217/08 , G06N3/126
摘要： A method of optimizing a very large scale integrated circuit design takes a circuit description which includes interconnected circuit components and characteristic variables assigned to the circuit components such as environmental, operational or process parameters, computes a first solution for the characteristic variables using a statistical analysis, and then computes a second solution for the characteristic variables using an evolutionary analysis seeded by the first solution. In the exemplary implementation the statistical analysis is a central composite design (CCD) and the evolutionary analysis is a genetic algorithm. Best case and worst case CCD solutions may be used to seed separate genetic algorithm runs and derive global best case and global worst case solutions. These solutions may be compared for sensitivity analysis. The method thereby provides significant reduction in time-to-solution with accurate simulation results.
摘要翻译：优化大规模集成电路设计的方法采用包括互连电路组件和分配给诸如环境，操作或过程参数的电路组件的特征变量的电路描述，使用统计分析来计算特征变量的第一解，然后使用第一个解决方案种子进化的分析计算特征变量的第二个解决方案。在示例性实施中，统计分析是中心复合设计（CCD），进化分析是遗传算法。最佳情况和最坏情况CCD解决方案可用于种子分离遗传算法运行，并得出全球最佳情况和全球最坏情况解决方案。可以将这些解决方案进行灵敏度分析。因此，该方法通过精确的模拟结果显着减少了解决方案的时间。

10. 发明申请

US20100229131A1 SWARM INTELLIGENCE FOR ELECTRICAL DESIGN SPACE MODELING AND OPTIMIZATION 有权
标题翻译：电气设计空间建模与优化的SWARM智能
公开(公告)号：US20100229131A1
公开(公告)日：2010-09-09
申请号：US12398535
申请日：2009-03-05
申请人： Moises Cases , Jinwoo Choi , Bhyrav Mutnury , Navraj Singh , Caleb J. Wesley
发明人： Moises Cases , Jinwoo Choi , Bhyrav Mutnury , Navraj Singh , Caleb J. Wesley
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/08
摘要： A method, system, and computer program product for exploring and optimizing an electrical design space. A computer receiving a design space assigns a plurality of initial values (random or predetermined) for optimizing the design space. A particle swarm containing a plurality of particles is created and an optimization of the design space is then performed using the assigned initial values. Following completion of optimization, the global best and personal best for each particle are updated. Velocity vectors and position vectors of the design space are then updated before the computer performs the optimization process again. The process loops, continually updating global and personal bests and velocity and position vectors until a termination criteria is reached. Upon reaching the termination criteria, the best fitness of each particle of the swarm is assigned as an optimized design space. In an alternate embodiment, the particle with the worst target fitness may be assigned.
摘要翻译：一种用于探索和优化电气设计空间的方法，系统和计算机程序产品。接收设计空间的计算机分配用于优化设计空间的多个初始值（随机或预定）。产生包含多个粒子的粒子群，然后使用分配的初始值来执行设计空间的优化。在优化完成后，更新每个粒子的全球最佳和个人最好的。然后在计算机再次执行优化处理之前更新设计空间的速度向量和位置向量。过程循环，持续更新全局和个人最佳状态以及速度和位置向量，直到达到终止标准。达到终止标准后，群体的每个粒子的最佳适应度被指定为优化的设计空间。在替代实施例中，可以分配具有最差目标适应度的粒子。

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