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1. 发明申请

US20070072374A1 SEMICONDUCTOR DEVICE 失效
公开(公告)号：US20070072374A1
公开(公告)日：2007-03-29
申请号：US11560109
申请日：2006-11-15
申请人： Mizuki ONO , Akira Nishiyama
发明人： Mizuki ONO , Akira Nishiyama
IPC分类号： H01L21/336
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/823456 , H01L21/823462 , H01L21/823475 , H01L21/823857 , H01L27/088 , H01L27/0922 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/785
摘要： A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.

2. 发明申请

US20070072478A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20070072478A1
公开(公告)日：2007-03-29
申请号：US11560061
申请日：2006-11-15
申请人： Mizuki ONO , Akira Nishiyama
发明人： Mizuki ONO , Akira Nishiyama
IPC分类号： H01R4/24
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/823456 , H01L21/823462 , H01L21/823475 , H01L21/823857 , H01L27/088 , H01L27/0922 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/785
摘要： A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.
摘要翻译：半导体器件包括半导体衬底，形成在衬底上的第一电路和连接到第一电路的第二电路作为其输入/输出部分并由比第一电路的电压高的电压供电，第一电路包括第一和第二场效应晶体管，第一晶体管的第一漏极区域伴随着第一负载电容，第二晶体管的第二漏极区域伴随着比第一负载电容小的第二负载电容，第一栅绝缘膜所述第一晶体管的平均相对介电常数高于所述第二晶体管的所述第二栅极绝缘膜的相对介电常数，从而实现高的运行速度。

3. 发明授权

US07364972B2 Semiconductor device 有权
公开(公告)号：US07364972B2
公开(公告)日：2008-04-29
申请号：US11560061
申请日：2006-11-15
申请人： Mizuki Ono , Akira Nishiyama
发明人： Mizuki Ono , Akira Nishiyama
IPC分类号： H01L21/8234
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/823456 , H01L21/823462 , H01L21/823475 , H01L21/823857 , H01L27/088 , H01L27/0922 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/785
摘要： A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.

4. 发明授权

US06847084B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06847084B2
公开(公告)日：2005-01-25
申请号：US10631792
申请日：2003-08-01
申请人： Mizuki Ono , Akira Nishiyama
发明人： Mizuki Ono , Akira Nishiyama
IPC分类号： H01L21/28 , H01L21/8234 , H01L27/088 , H01L29/51 , H01L29/78 , H01L29/72
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/823456 , H01L21/823462 , H01L21/823475 , H01L21/823857 , H01L27/088 , H01L27/0922 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/785
摘要： A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.
摘要翻译：半导体器件包括半导体衬底，形成在衬底上的第一电路和连接到第一电路的第二电路作为其输入/输出部分并由比第一电路的电压高的电压供电，第一电路包括第一和第二场效应晶体管，第一晶体管的第一漏极区域伴随着第一负载电容，第二晶体管的第二漏极区域伴随着比第一负载电容小的第二负载电容，第一栅绝缘膜所述第一晶体管的平均相对介电常数高于所述第二晶体管的所述第二栅极绝缘膜的相对介电常数，从而实现高的运行速度。

5. 发明授权

US06690047B2 MIS transistor having a large driving current and method for producing the same 失效
标题翻译：具有大驱动电流的MIS晶体管及其制造方法
公开(公告)号：US06690047B2
公开(公告)日：2004-02-10
申请号：US10132175
申请日：2002-04-26
申请人： Yukihito Oowaki , Mizuki Ono , Mitsuhiro Noguchi , Daisaburo Takashima , Akira Nishiyama
发明人： Yukihito Oowaki , Mizuki Ono , Mitsuhiro Noguchi , Daisaburo Takashima , Akira Nishiyama
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66621 , H01L29/78
摘要： In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.
摘要翻译：在MIS晶体管中，形成在半导体基板1上的源极/漏极区域（S / D扩散层）的上表面布置成比半导体衬底上的沟道平面更靠近栅电极，源极/漏极区域的顶表面漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。在该晶体管中，在半导体衬底的表面中选择性地形成沟槽，并且可以将沉积在沟槽中的多晶硅用作掩模，以形成用作源极/漏极区域的杂质扩散层，以层压并形成栅极绝缘膜的高介电膜和栅电极。或者，可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。因此，可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。

6. 发明授权

US07303965B2 MIS transistor and method for producing same 失效
标题翻译： MIS晶体管及其制造方法
公开(公告)号：US07303965B2
公开(公告)日：2007-12-04
申请号：US09879208
申请日：2001-06-13
申请人： Yukihito Oowaki , Mizuki Ono , Mitsuhiro Noguchi , Daisaburo Takashima , Akira Nishiyama
发明人： Yukihito Oowaki , Mizuki Ono , Mitsuhiro Noguchi , Daisaburo Takashima , Akira Nishiyama
IPC分类号： H01L21/33 , H01L21/3205 , H01L31/00
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66621 , H01L29/78
摘要： In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.
摘要翻译：在MIS晶体管中，形成在半导体基板1上的源极/漏极区域（S / D扩散层）的上表面布置成比半导体衬底上的沟道平面更靠近栅电极，源极/漏极区域的顶表面漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。在该晶体管中，在半导体衬底的表面中选择性地形成沟槽，并且可以将沉积在沟槽中的多晶硅用作掩模，以形成用作源极/漏极区域的杂质扩散层，以层压并形成栅极绝缘膜的高介电膜和栅电极。或者，可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。因此，可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。

7. 发明申请

US20050040461A1 Semiconductor device 审中-公开
公开(公告)号：US20050040461A1
公开(公告)日：2005-02-24
申请号：US10951651
申请日：2004-09-29
申请人： Mizuki Ono , Akira Nishiyama
发明人： Mizuki Ono , Akira Nishiyama
IPC分类号： H01L21/28 , H01L21/8234 , H01L27/088 , H01L29/51 , H01L29/78 , H01L29/76
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/823456 , H01L21/823462 , H01L21/823475 , H01L21/823857 , H01L27/088 , H01L27/0922 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/785
摘要： A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.

8. 发明授权

US06278165B1 MIS transistor having a large driving current and method for producing the same 有权
标题翻译：具有大驱动电流的MIS晶体管及其制造方法
公开(公告)号：US06278165B1
公开(公告)日：2001-08-21
申请号：US09340149
申请日：1999-06-28
申请人： Yukihito Oowaki , Mizuki Ono , Mitsuhiro Noguchi , Daisaburo Takashima , Akira Nishiyama
发明人： Yukihito Oowaki , Mizuki Ono , Mitsuhiro Noguchi , Daisaburo Takashima , Akira Nishiyama
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66621 , H01L29/78
摘要： In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.
摘要翻译：在MIS晶体管中，形成在半导体基板1上的源极/漏极区域（S / D扩散层）的上表面布置成比半导体衬底上的沟道平面更靠近栅电极，源极/漏极区域的顶表面漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。在该晶体管中，在半导体衬底的表面中选择性地形成沟槽，并且可以将沉积在沟槽中的多晶硅用作掩模，以形成用作源极/漏极区域的杂质扩散层，以层压并形成栅极绝缘膜的高介电膜和栅电极。或者，可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。因此，可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。

9. 发明授权

US07422944B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07422944B2
公开(公告)日：2008-09-09
申请号：US11560109
申请日：2006-11-15
申请人： Mizuki Ono , Akira Nishiyama
发明人： Mizuki Ono , Akira Nishiyama
IPC分类号： H01L21/8234
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/823456 , H01L21/823462 , H01L21/823475 , H01L21/823857 , H01L27/088 , H01L27/0922 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/785
摘要： A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.
摘要翻译：半导体器件包括半导体衬底，形成在衬底上的第一电路和连接到第一电路的第二电路作为其输入/输出部分并由比第一电路的电压高的电压供电，第一电路包括第一和第二场效应晶体管，第一晶体管的第一漏极区域伴随着第一负载电容，第二晶体管的第二漏极区域伴随着比第一负载电容小的第二负载电容，第一栅绝缘膜所述第一晶体管的平均相对介电常数高于所述第二晶体管的所述第二栅极绝缘膜的相对介电常数，从而实现高的运行速度。

10. 发明授权

US07087969B2 Complementary field effect transistor and its manufacturing method 有权
标题翻译：互补场效应晶体管及其制造方法
公开(公告)号：US07087969B2
公开(公告)日：2006-08-08
申请号：US10760501
申请日：2004-01-21
申请人： Akira Nishiyama , Mizuki Ono , Masato Koyama , Takamitsu Ishihara
发明人： Akira Nishiyama , Mizuki Ono , Masato Koyama , Takamitsu Ishihara
IPC分类号： H01L29/76 , H01L31/119
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/823842 , H01L29/518
摘要： A complementary field effect transistor comprises: a semiconductor substrate; an n-type field effect transistor provided on the semiconductor substrate; and a p-type field effect transistor provided on the semiconductor substrate. The n-type field effect transistor has: a first gate insulating film containing an oxide including an element selected from the group consisting of group IV metals and Lanthanoid metals, and further containing a compound of the element and a group III element; a first gate electrode provided on the first gate insulating film; and n-type source and drain regions formed on both sides of the first gate electrode. The p-type field effect transistor has: a second gate insulating film containing an oxide including an element selected from the group consisting of group IV metals and Lanthanoid metals, and including substantially no positive charge; a second gate electrode provided on the second gate insulating film; and p-type source and drain regions provided on both sides of the second gate electrode.
摘要翻译：互补场效应晶体管包括：半导体衬底; 设置在半导体衬底上的n型场效应晶体管; 以及设置在半导体基板上的p型场效应晶体管。 n型场效应晶体管具有：包含含有选自IV族金属和镧系金属的元素的氧化物的第一栅极绝缘膜，并且还含有元素和III族元素的化合物; 设置在所述第一栅极绝缘膜上的第一栅电极; 以及形成在第一栅电极的两侧上的n型源区和漏区。 p型场效应晶体管具有：第二栅极绝缘膜，其含有包含选自第Ⅳ族金属和镧系金属的元素的氧化物，并且基本上不含正电荷; 设置在所述第二栅极绝缘膜上的第二栅电极; 以及设置在第二栅电极的两侧的p型源区和漏区。

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