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1. 发明授权

US06746969B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06746969B2
公开(公告)日：2004-06-08
申请号：US09982003
申请日：2001-10-19
申请人： Miyoko Shimada , Hideshi Miyajima , Rempei Nakata , Hideto Matsuyama , Katsuya Okumura , Masahiko Hasunuma , Nobuo Hayasaka
发明人： Miyoko Shimada , Hideshi Miyajima , Rempei Nakata , Hideto Matsuyama , Katsuya Okumura , Masahiko Hasunuma , Nobuo Hayasaka
IPC分类号： H01L2131
CPC分类号： H01L21/02351 , H01L21/02126 , H01L21/02137 , H01L21/02312 , H01L21/02337 , H01L21/2636 , H01L21/3122 , H01L21/316 , H01L21/76825 , H01L21/76828 , H01L21/76834
摘要： A method of manufacturing a semiconductor device comprises preparing a substrate to be treated, and forming an insulation film above the substrate, which includes applying an insulation film raw material above the substrate, the insulation film raw material including a substance or a precursor of the substance, the insulation film comprising the substance, curing the insulation film raw material by irradiating an electron beam on the substrate while heating the substrate in a reactor chamber, changing at least one of parameter selected from the group consisting of pressure in the reactor chamber, temperature of the substrate, type of gas having the substrate exposed thereto, flow rate of gas introduced into the reactor chamber, position of the substrate, and quantity of electrons incident to the substrate per unit time when the electron beam is being irradiated on the substrate.
摘要翻译：一种制造半导体器件的方法包括：准备待处理的衬底，以及在衬底上方形成绝缘膜，该绝缘膜包括在衬底上施加绝缘膜原料，所述绝缘膜原料包括物质或物质的前体所述绝缘膜包含该物质，通过在反应器室中加热基板同时在基板上照射电子束来固化绝缘膜原料，改变选自反应器室中的压力，温度的基板，当电子束被照射在基板上时，具有暴露于其中的基板的气体类型，引入反应室的气体流量，基板的位置和每单位时间入射到基板的电子量。

2. 发明授权

US06436849B1 Method for manufacturing semiconductor device having low dielectric constant insulating film, wafer processing equipment and wafer storing box used in this method 失效
标题翻译：用于制造具有低介电常数绝缘膜的半导体器件的方法，该方法中使用的晶片加工设备和晶片储存盒
公开(公告)号：US06436849B1
公开(公告)日：2002-08-20
申请号：US09963385
申请日：2001-09-27
申请人： Masahiko Hasunuma , Hideshi Miyajima , Hisashi Kaneko , Rempei Nakata
发明人： Masahiko Hasunuma , Hideshi Miyajima , Hisashi Kaneko , Rempei Nakata
IPC分类号： H01L2131
CPC分类号： H01L21/67253 , H01L21/67017 , H01L21/76828
摘要： A method for manufacturing a semiconductor device, comprising controlling a humidity in an atmosphere around a low dielectric constant insulating film at 30% or less, during a processing period and a transfer period between processing equipments, in which at least a part of said low dielectric constant insulating film is exposed to the atmosphere.
摘要翻译：一种制造半导体器件的方法，包括在处理期间和处理设备之间的转移期间，在低介电常数绝缘膜周围的气氛中控制30％以下的湿度，其中至少部分所述低电介质恒定绝缘膜暴露在大气中。

3. 发明授权

US06946387B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06946387B2
公开(公告)日：2005-09-20
申请号：US10650974
申请日：2003-08-29
申请人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
发明人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
IPC分类号： H01L21/285 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76867 , H01L21/2855 , H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76859 , H01L21/76864 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L21/76889
摘要： A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在具有布线层的Si衬底上形成绝缘膜，形成与布线层连接的接触孔和绝缘膜中的布线槽，用Si 膜，依次在基板上形成Al膜和Ti膜，进行热处理，从而将Al膜替代为Ti膜，并使Si膜被Ti膜吸收，由此填充接触孔和Al膜的布线槽，除去由Ti膜和多余Ti吸收Si膜形成的由Ti硅化物构成的Ti / Ti硅化物，由此用Al塞填充接触孔，并填充布线槽与Al接线。

4. 发明授权

US06673704B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06673704B2
公开(公告)日：2004-01-06
申请号：US10189598
申请日：2002-07-08
申请人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
发明人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
IPC分类号： H01L2140
CPC分类号： H01L21/76867 , H01L21/2855 , H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76859 , H01L21/76864 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L21/76889
摘要： A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在具有布线层的Si衬底上形成绝缘膜，形成与布线层连接的接触孔和绝缘膜中的布线槽，用Si 膜，依次在基板上形成Al膜和Ti膜，进行热处理，从而将Al膜替代为Ti膜，并使Si膜被Ti膜吸收，由此填充接触孔和Al膜的布线槽，除去由Ti膜和多余Ti吸收Si膜形成的由Ti硅化物构成的Ti / Ti硅化物，由此用Al塞填充接触孔，并填充布线槽与Al接线。

5. 发明授权

US06440843B1 Semiconductor device and method for manufacturing the same 失效
公开(公告)号：US06440843B1
公开(公告)日：2002-08-27
申请号：US09556961
申请日：2000-04-21
申请人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
发明人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
IPC分类号： H01L2358
CPC分类号： H01L21/76867 , H01L21/2855 , H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76859 , H01L21/76864 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L21/76889
摘要： A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

6. 发明授权

US6071810A Method of filling contact holes and wiring grooves of a semiconductor device 失效
标题翻译：填充半导体器件的接触孔和布线槽的方法
公开(公告)号：US6071810A
公开(公告)日：2000-06-06
申请号：US997328
申请日：1997-12-23
申请人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
发明人： Junichi Wada , Atsuko Sakata , Tomio Katata , Takamasa Usui , Masahiko Hasunuma , Hideki Shibata , Hisashi Kaneko , Nobuo Hayasaka , Katsuya Okumura
IPC分类号： H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76867 , H01L21/2855 , H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76859 , H01L21/76864 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L21/76889
摘要： A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在具有布线层的Si衬底上形成绝缘膜，形成与布线层连接的接触孔和绝缘膜中的布线槽，用Si 膜，依次在基板上形成Al膜和Ti膜，进行热处理，从而将Al膜替代为Ti膜，并使Si膜被Ti膜吸收，由此填充接触孔和Al膜的布线槽，除去由Ti膜和多余Ti吸收Si膜形成的由Ti硅化物构成的Ti / Ti硅化物，由此用Al塞填充接触孔，并填充布线槽与Al接线。

7. 发明授权

US06306756B1 Method for production of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US06306756B1
公开(公告)日：2001-10-23
申请号：US09580922
申请日：2000-05-26
申请人： Masahiko Hasunuma , Sachiyo Ito , Keizo Shimamura , Hisashi Kaneko , Nobuo Hayasaka , Junsei Tsutsumi , Akihiro Kajita , Junichi Wada , Haruo Okano
发明人： Masahiko Hasunuma , Sachiyo Ito , Keizo Shimamura , Hisashi Kaneko , Nobuo Hayasaka , Junsei Tsutsumi , Akihiro Kajita , Junichi Wada , Haruo Okano
IPC分类号： H01L214763
CPC分类号： H01L21/76882
摘要： A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film and causing never melting to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently. During the heat treatment, a reducing gas is supplied in addition to the oxidizing gas to induce a local oxidation-reduction reaction and fluidify and/or flow the conductive film and consequently accomplish the embodiment of the conductive film in the trenches. The formation of the interconnection is also accomplished by forming a conductive film on the surface of a semiconducting substrate having trenches formed therein, exerting thereon uniaxial stress from above the semiconducting substrate, heat treating the formed conductive film thereby flowing the conductive film, to fill the trenches, and polishing the surface of the semiconducting substrate.
摘要翻译：公开了一种制造半导体器件的方法，该半导体器件具有形成在半导体衬底中的电极线，其包括制备半导体衬底，该半导体衬底具有在预定形成电极线的区域中预先形成的沟槽和/或接触孔，形成导电膜主要是在半导体基板的表面上选自Cu，Ag和Au中的至少一个元件，在至少供给氧化气体的同时对叠加的Cu膜进行热处理，从而使Cu膜流动，从而不会熔化以填充沟槽和/或接触孔，并且通过抛光导电膜的掉落在电极线的区域外部并且完成电极线的部分去除。在热处理期间，除了氧化气体之外还提供还原气体以引起局部氧化还原反应，并使导电膜流通和/或流动，从而完成沟槽中导电膜的实施例。互连的形成还可以通过在其上形成有沟槽的半导体衬底的表面上形成导电膜，在半导体衬底上方施加单轴应力，热处理形成的导电膜从而使导电膜流动，从而填充沟槽，并抛光半导体衬底的表面。

8. 发明授权

US6090701A Method for production of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US6090701A
公开(公告)日：2000-07-18
申请号：US521088
申请日：1995-06-20
申请人： Masahiko Hasunuma , Sachiyo Ito , Keizo Shimamura , Hisashi Kaneko , Nobuo Hayasaka , Junsei Tsutsumi , Akihiro Kajita , Junichi Wada , Haruo Okano
发明人： Masahiko Hasunuma , Sachiyo Ito , Keizo Shimamura , Hisashi Kaneko , Nobuo Hayasaka , Junsei Tsutsumi , Akihiro Kajita , Junichi Wada , Haruo Okano
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76882
摘要： A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently. During the heat treatment, a reducing gas is supplied in addition to the oxidizing gas to induce a local oxidation-reduction reaction and fluidify and/or flow the conductive film and consequently accomplish the embodiment of the conductive film in the trenches.
摘要翻译：公开了一种制造半导体器件的方法，该半导体器件具有形成在半导体衬底中的电极线，其包括制备半导体衬底，该半导体衬底具有在预定形成电极线的区域中预先形成的沟槽和/或接触孔，形成导电膜主要是在半导体基板的表面上选自Cu，Ag和Au中的至少一个元件，在至少供给氧化气体的同时对叠加的Cu膜进行热处理，从而使Cu膜流过以填充沟槽和/或接触孔，并且通过抛光导电膜的掉在电极线的区域外部并且完成电极线的部分去除。在热处理期间，除了氧化气体之外还提供还原气体以引起局部氧化还原反应，并使导电膜流通和/或流动，从而完成沟槽中导电膜的实施例。

9. 发明授权

US07921401B2 Stress analysis method, wiring structure design method, program, and semiconductor device production method 有权
标题翻译：应力分析方法，接线结构设计方法，程序和半导体器件的制造方法
公开(公告)号：US07921401B2
公开(公告)日：2011-04-05
申请号：US11703218
申请日：2007-02-07
申请人： Sachiyo Ito , Masahiko Hasunuma , Hisashi Kaneko
发明人： Sachiyo Ito , Masahiko Hasunuma , Hisashi Kaneko
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： G06F17/5018 , G06F17/5068 , G06F2217/80 , H01L2924/0002 , H01L2924/00
摘要： A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area are compounded, about each of the plurality of analysis areas on the basis of wiring structure data for each of the plurality of analysis areas, and creating, by using a stress analysis unit, a three-dimensional model of a finite element method which uses each analysis area as an element, to apply the composite property to each element, and to perform a stress analysis.
摘要翻译：提供一种应力分析方法，包括：通过使用分割单元将芯片的内部划分为多个分析区域，通过使用复合特性导出单元导出多个分析区域的物理属性值的复合特性基于多个分析区域中的每一个的布线结构数据，分析包括在分析区域中的材料，并且基于多个分析区域中的每一个，分别对每个分析区域进行复合，并且通过使用应力分析单元来创建三维模型使用每个分析区域作为元素的有限元法，将复合属性应用于每个元素，并进行应力分析。

10. 发明授权

US07872353B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07872353B2
公开(公告)日：2011-01-18
申请号：US11964336
申请日：2007-12-26
申请人： Sachiyo Ito , Masahiko Hasunuma
发明人： Sachiyo Ito , Masahiko Hasunuma
IPC分类号： H01L23/52
CPC分类号： H01L23/53295 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including at least two layers of interlayer-insulator-films stacked above a substrate and at least partially formed by a low-relative-dielectric-constant-film having a relative-dielectric-constant of 3.4 or less respectively, a plurality of wirings provided at least one within each of the interlayer-insulator-film and at least partially located within the low-relative-dielectric-constant-films, a plurality of plugs provided at least one within each of the interlayer-insulator-film and connected to a lower part of the wirings, and a plurality of reinforcement members provided at least one within each of the interlayer-insulator-film with being separated from the wirings at a predetermined interval, electrically cut from the wirings and the plugs, and at least partially located within the low-relative-dielectric-constant-films, and wherein, the interlayer-insulator-films, the wirings, the plugs, and the reinforcement members satisfy a predetermined relation for each of the interlayer-insulator-film.
摘要翻译：一种半导体器件，包括层叠在衬底上的至少两层层间绝缘膜，并且至少部分由相对介电常数为3.4以下的低相对介电常数膜形成，多个布线在每个层间绝缘膜内提供至少一个，并且至少部分地位于低相对介电常数膜内;多个插塞，其设置在每个层间绝缘膜内至少一个并连接连接到布线的下部，以及多个加强构件，其在每个层间绝缘体膜内设置有至少一个预定间隔的布线，从布线和插塞电切割，并且至少部分位于低相对介电常数膜内，并且其中层间绝缘膜，布线，插塞和加强件满足关于每个层间绝缘膜。

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