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1. 发明授权

US06306756B1 Method for production of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US06306756B1
公开(公告)日：2001-10-23
申请号：US09580922
申请日：2000-05-26
申请人： Masahiko Hasunuma , Sachiyo Ito , Keizo Shimamura , Hisashi Kaneko , Nobuo Hayasaka , Junsei Tsutsumi , Akihiro Kajita , Junichi Wada , Haruo Okano
发明人： Masahiko Hasunuma , Sachiyo Ito , Keizo Shimamura , Hisashi Kaneko , Nobuo Hayasaka , Junsei Tsutsumi , Akihiro Kajita , Junichi Wada , Haruo Okano
IPC分类号： H01L214763
CPC分类号： H01L21/76882
摘要： A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film and causing never melting to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently. During the heat treatment, a reducing gas is supplied in addition to the oxidizing gas to induce a local oxidation-reduction reaction and fluidify and/or flow the conductive film and consequently accomplish the embodiment of the conductive film in the trenches. The formation of the interconnection is also accomplished by forming a conductive film on the surface of a semiconducting substrate having trenches formed therein, exerting thereon uniaxial stress from above the semiconducting substrate, heat treating the formed conductive film thereby flowing the conductive film, to fill the trenches, and polishing the surface of the semiconducting substrate.
摘要翻译：公开了一种制造半导体器件的方法，该半导体器件具有形成在半导体衬底中的电极线，其包括制备半导体衬底，该半导体衬底具有在预定形成电极线的区域中预先形成的沟槽和/或接触孔，形成导电膜主要是在半导体基板的表面上选自Cu，Ag和Au中的至少一个元件，在至少供给氧化气体的同时对叠加的Cu膜进行热处理，从而使Cu膜流动，从而不会熔化以填充沟槽和/或接触孔，并且通过抛光导电膜的掉落在电极线的区域外部并且完成电极线的部分去除。在热处理期间，除了氧化气体之外还提供还原气体以引起局部氧化还原反应，并使导电膜流通和/或流动，从而完成沟槽中导电膜的实施例。互连的形成还可以通过在其上形成有沟槽的半导体衬底的表面上形成导电膜，在半导体衬底上方施加单轴应力，热处理形成的导电膜从而使导电膜流动，从而填充沟槽，并抛光半导体衬底的表面。

2. 发明授权

US6090701A Method for production of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US6090701A
公开(公告)日：2000-07-18
申请号：US521088
申请日：1995-06-20
申请人： Masahiko Hasunuma , Sachiyo Ito , Keizo Shimamura , Hisashi Kaneko , Nobuo Hayasaka , Junsei Tsutsumi , Akihiro Kajita , Junichi Wada , Haruo Okano
发明人： Masahiko Hasunuma , Sachiyo Ito , Keizo Shimamura , Hisashi Kaneko , Nobuo Hayasaka , Junsei Tsutsumi , Akihiro Kajita , Junichi Wada , Haruo Okano
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76882
摘要： A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently. During the heat treatment, a reducing gas is supplied in addition to the oxidizing gas to induce a local oxidation-reduction reaction and fluidify and/or flow the conductive film and consequently accomplish the embodiment of the conductive film in the trenches.
摘要翻译：公开了一种制造半导体器件的方法，该半导体器件具有形成在半导体衬底中的电极线，其包括制备半导体衬底，该半导体衬底具有在预定形成电极线的区域中预先形成的沟槽和/或接触孔，形成导电膜主要是在半导体基板的表面上选自Cu，Ag和Au中的至少一个元件，在至少供给氧化气体的同时对叠加的Cu膜进行热处理，从而使Cu膜流过以填充沟槽和/或接触孔，并且通过抛光导电膜的掉在电极线的区域外部并且完成电极线的部分去除。在热处理期间，除了氧化气体之外还提供还原气体以引起局部氧化还原反应，并使导电膜流通和/或流动，从而完成沟槽中导电膜的实施例。

3. 发明授权

US06001461A Electronic parts and manufacturing method thereof 失效
标题翻译：电子零件及其制造方法
公开(公告)号：US06001461A
公开(公告)日：1999-12-14
申请号：US771388
申请日：1996-12-19
申请人： Hiroshi Toyoda , Hisashi Kaneko , Masahiko Hasunuma , Takashi Kawanoue , Hiroshi Tomita , Akihiro Kajita , Masami Miyauchi , Takashi Kawakubo , Sachiyo Ito
发明人： Hiroshi Toyoda , Hisashi Kaneko , Masahiko Hasunuma , Takashi Kawanoue , Hiroshi Tomita , Akihiro Kajita , Masami Miyauchi , Takashi Kawakubo , Sachiyo Ito
IPC分类号： H01L21/3205 , H01L23/528 , H01L23/532 , B32B9/00
CPC分类号： H01L23/532 , H01L21/32051 , H01L23/5283 , H01L23/53223 , H01L2924/0002 , Y10T428/2457 , Y10T428/24926
摘要： An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary. A method for manufacturing an electronic part, comprising the step of depositing a conductor layer which is mainly formed of one selected from Al and Cu on a substrate via an insulative layer, a barrier layer, a contact layer or an amorphous thin film layer wherein one element selected from Ga, In, Cd, Bi, Pb, Sn and Tl is supplied before or during the deposition of the conductor layer.
摘要翻译：一种电子部件，包括形成在基板上的非晶薄膜; 以及形成在所述非晶薄膜的表面上的金属布线; 其中对应于在非晶薄膜的衍射测量中出现的晕轮图案的峰值的原子间距离大致与由金属布线的第一最接近的原子间距离限定的特定晶面的间隔相匹配。一种电子部件，其具有由高取向晶体形成的金属布线，其中所有晶界的一半以上是由倾斜，旋转及其组合在取向方向上的相位差取向为10°以下的晶界之一限定的小角度晶界相邻晶粒的轴; SIGMA值为10以下的重合边界; 晶界与重合边界的相对误差为3°以下。一种电子部件的制造方法，其特征在于，包括以下步骤：通过绝缘层，阻挡层，接触层或无定形薄膜层，在基板上沉积主要由选自Al和Cu的一个导体层形成的步骤，其中一个选自Ga，In，Cd，Bi，Pb，Sn和Tl的元素在导体层的沉积之前或期间提供。

4. 发明授权

US5709958A Electronic parts 失效
标题翻译：电子零件
公开(公告)号：US5709958A
公开(公告)日：1998-01-20
申请号：US451528
申请日：1995-05-26
申请人： Hiroshi Toyoda , Hisashi Kaneko , Masahiko Hasunuma , Takashi Kawanoue , Hiroshi Tomita , Akihiro Kajita , Masami Miyauchi , Takashi Kawakubo , Sachiyo Ito
发明人： Hiroshi Toyoda , Hisashi Kaneko , Masahiko Hasunuma , Takashi Kawanoue , Hiroshi Tomita , Akihiro Kajita , Masami Miyauchi , Takashi Kawakubo , Sachiyo Ito
IPC分类号： H01L21/3205 , H01L23/528 , H01L23/532 , H01L29/43
CPC分类号： H01L21/32051 , H01L23/5283 , H01L23/532 , H01L23/53223 , H01L2924/0002 , Y10T428/12528 , Y10T428/12674 , Y10T428/12681
摘要： An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary. A method for manufacturing an electronic part, comprising the step of depositing a conductor layer which is mainly formed of one selected from Al and Cu on a substrate via an insulative layer, a barrier layer, a contact layer or an amorphous thin film layer wherein one element selected from Ga, In, Cd, Bi, Pb, Sn and Tl is supplied before or during the deposition of the conductor layer.
摘要翻译：一种电子部件，包括形成在基板上的非晶薄膜; 以及形成在所述非晶薄膜的表面上的金属布线; 其中对应于在非晶薄膜的衍射测量中出现的晕轮图案的峰值的原子间距离大致与由金属布线的第一最接近的原子间距离限定的特定晶面的间隔相匹配。一种电子部件，其具有由高取向晶体形成的金属布线，其中所有晶界的一半以上是由倾斜，旋转及其组合在取向方向上的相位差取向为10°以下的晶界之一限定的小角度晶界相邻晶粒的轴; SIGMA值为10以下的重合边界; 晶界与重合边界的相对误差为3°以下。一种电子部件的制造方法，其特征在于，包括以下步骤：通过绝缘层，阻挡层，接触层或无定形薄膜层，在基板上沉积主要由选自Al和Cu的一个导体层形成的步骤，其中一个选自Ga，In，Cd，Bi，Pb，Sn和Tl的元素在导体层的沉积之前或期间提供。

5. 发明授权

US06291891B1 Semiconductor device manufacturing method and semiconductor device 有权
公开(公告)号：US06291891B1
公开(公告)日：2001-09-18
申请号：US09228642
申请日：1999-01-12
申请人： Kazuyuki Higashi , Noriaki Matsunaga , Akihiro Kajita , Tetsuo Matsuda , Tadashi Iijima , Hisashi Kaneko , Hideki Shibata , Naofumi Nakamura , Minakshisundaran Balasubramanian Anand , Tadashi Matsuno , Katsuya Okumura
发明人： Kazuyuki Higashi , Noriaki Matsunaga , Akihiro Kajita , Tetsuo Matsuda , Tadashi Iijima , Hisashi Kaneko , Hideki Shibata , Naofumi Nakamura , Minakshisundaran Balasubramanian Anand , Tadashi Matsuno , Katsuya Okumura
IPC分类号： H01L2348
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/76807 , H01L21/76814 , H01L21/76819 , H01L21/76831 , H01L21/76834 , H01L21/76835 , H01L21/76844 , H01L21/76849 , H01L21/76885 , H01L21/76897 , H01L23/5226 , H01L2221/1026 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

6. 发明授权

US06555925B1 Semiconductor device and producing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06555925B1
公开(公告)日：2003-04-29
申请号：US09517187
申请日：2000-03-02
申请人： Kazuyuki Higashi , Noriaki Matsunaga , Akihiro Kajita , Tamao Takase , Hisashi Kaneko , Hideki Shibata
发明人： Kazuyuki Higashi , Noriaki Matsunaga , Akihiro Kajita , Tamao Takase , Hisashi Kaneko , Hideki Shibata
IPC分类号： H01L23544
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The present invention is a method of producing a semiconductor device in which at least one alignment mark to be used in an exposure process of a lithographic process is formed of a wiring material which is copper or includes copper as a main component, and the alignment mark is formed entirely in an area outside an area where dicing is to be executed.
摘要翻译：本发明是一种制造半导体器件的方法，其中在光刻工艺的曝光处理中使用的至少一个对准标记由铜或者铜作为主要成分的布线材料形成，并且对准标记完全在要执行切割的区域外的区域中形成。

7. 发明授权

US06368951B2 Semiconductor device manufacturing method and semiconductor device 有权
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US06368951B2
公开(公告)日：2002-04-09
申请号：US09903992
申请日：2001-07-13
申请人： Kazuyuki Higashi , Noriaki Matsunaga , Akihiro Kajita , Tetsuo Matsuda , Tadashi Iijima , Hisashi Kaneko , Hideki Shibata , Naofumi Nakamura , Minakshisundaran Balasubramanian Anand , Tadashi Matsuno , Katsuya Okumura
发明人： Kazuyuki Higashi , Noriaki Matsunaga , Akihiro Kajita , Tetsuo Matsuda , Tadashi Iijima , Hisashi Kaneko , Hideki Shibata , Naofumi Nakamura , Minakshisundaran Balasubramanian Anand , Tadashi Matsuno , Katsuya Okumura
IPC分类号： H01L214763
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/76807 , H01L21/76814 , H01L21/76819 , H01L21/76831 , H01L21/76834 , H01L21/76835 , H01L21/76844 , H01L21/76849 , H01L21/76885 , H01L21/76897 , H01L23/5226 , H01L2221/1026 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.
摘要翻译：一种半导体器件的制造方法，其特征在于，在形成于半导体衬底上的第一绝缘膜上形成沟槽，在所述沟槽中形成下层配线的工序，在所述半导体衬底上形成至少一层导体层，在导电层上形成至少一层薄膜层的步骤，通过图案化薄膜形成硬掩模的步骤，通过使用硬掩模作为蚀刻掩模蚀刻导电层的步骤，以及形成导电柱状结构，其上表面被硬掩模覆盖在下层布线上;在半导体基板上形成第二绝缘膜以使柱状结构被埋设的步骤，形成至少暴露硬掩模的布线沟槽以及在去除硬掩模之后将导体埋入布线沟槽中的步骤，以及在布线沟槽中形成上层布线。

8. 发明授权

US06342444B1 Method of forming diffusion barrier for copper interconnects 有权
标题翻译：形成铜互连的扩散阻挡层的方法
公开(公告)号：US06342444B1
公开(公告)日：2002-01-29
申请号：US09522595
申请日：2000-03-10
申请人： Kazuyuki Higashi , Noriaki Matsunaga , Hiroshi Toyoda , Akihiro Kajita , Tetsuo Matsuda , Hisashi Kaneko
发明人： Kazuyuki Higashi , Noriaki Matsunaga , Hiroshi Toyoda , Akihiro Kajita , Tetsuo Matsuda , Hisashi Kaneko
IPC分类号： H01L214763
CPC分类号： H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76858 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A TiN film is selectively formed as a barrier layer on a Cu metal layer by selective removal of a Ti metal layer on the Si metal layer after the following steps of selectively forming a Si metal layer as an etching mask on an insulation film, forming a trench pattern by selective removal of the insulation film using the Si metal layer, forming a Cu metal layer in the trench pattern with the Si metal layer remained, forming the Ti metal layer on the Si metal layer and the Cu metal layer as a barrier material with a different kind of eutectic reaction with Cu from the reaction with the etching mask by heat-treatment in an atmosphere of nitrogen, and selectively nitriding the Ti metal layer on the Cu metal layer by heat-treatment of the Ti metal layer in an atmosphere of nitrogen.
摘要翻译：通过在绝缘膜上选择性地形成Si金属层作为蚀刻掩模的以下步骤之后，通过选择性地除去Si金属层上的Ti金属层，在Cu金属层上选择性地形成TiN膜作为阻挡层，形成沟槽图案，通过使用Si金属层选择性去除绝缘膜，在沟槽图案中形成具有Si金属层的Cu金属层，在Si金属层上形成Ti金属层，将Cu金属层形成为阻挡材料在氮气气氛中通过热处理与与蚀刻掩模的反应与Cu的不同种类的共晶反应，并且通过在气氛中热处理Ti金属层来选择性地氮化Cu金属层上的Ti金属层的氮气。

9. 发明授权

US5953634A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5953634A
公开(公告)日：1999-09-14
申请号：US600026
申请日：1996-02-12
申请人： Akihiro Kajita , Hisashi Kaneko
发明人： Akihiro Kajita , Hisashi Kaneko
IPC分类号： C23C16/02 , C23C16/18 , C23C16/44 , C23C16/448 , C23C16/455 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/44
CPC分类号： C23C16/45565 , C23C16/0272 , C23C16/18 , C23C16/4412 , C23C16/4481 , C23C16/45512 , C23C16/45523 , H01L21/28556 , H01L21/32051 , H01L21/76843 , H01L21/76856 , H01L21/76877
摘要： A method of manufacturing a semiconductor device comprising the steps of, forming a diffusion-preventing thin film on a substrate, performing a first vapor deposition by supplying a source gas comprising a copper-containing organometallic compound and an oxidizing gas over the diffusion-preventing thin film thereby to allow a first conductive thin film containing copper as a main component and a trace of oxygen to be grown through a chemical vapor deposition, performing a second vapor deposition by supplying the source gas without supplying the oxidizing gas thereby to allow a second conductive thin film mainly containing copper to be grown through a chemical vapor deposition, and heat-treating the first and second conductive thin films at a temperature which is higher than those employed in the first and second vapor depositions.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在衬底上形成防扩散薄膜，通过在扩散防止薄膜上提供包含含铜有机金属化合物和氧化气体的源气体，进行第一气相沉积从而允许以铜为主要成分的第一导电薄膜和通过化学气相沉积生长的氧痕迹，通过供应源气体而不供应氧化气体进行第二气相沉积，从而允许第二导电主要含有通过化学气相沉积生长的铜的薄膜，并且在比第一和第二蒸气沉积中采用的温度高的温度下热处理第一和第二导电薄膜。

10. 发明授权

US08759983B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08759983B2
公开(公告)日：2014-06-24
申请号：US12361979
申请日：2009-01-29
申请人： Makoto Wada , Akihiro Kajita , Kazuyuki Higashi
发明人： Makoto Wada , Akihiro Kajita , Kazuyuki Higashi
IPC分类号： H01L29/41
CPC分类号： H01L21/76802 , H01L21/76816 , H01L21/76834 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region.
摘要翻译：根据一个实施例的半导体器件包括：设置有半导体元件的半导体衬底; 形成在所述半导体衬底之上的连接构件，构造成电连接上导电构件和下导电构件; 形成在与所述连接构件相同的层中的第一绝缘膜; 形成在所述连接构件上的布线，所述布线包括第一区域和第二区域，所述第一区域与所述连接构件的上表面的一部分接触，所述第二区域位于所述第一区域上，并且宽度大于第一区域; 以及形成在所述第一绝缘膜上以与所述布线的所述第一区域的至少一部分和所述第二区域的底表面接触的第二绝缘膜。

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