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1. 发明授权

US5047815A Semiconductor memory device having a trench-stacked capacitor 失效
标题翻译：具有沟槽叠层电容器的半导体存储器件
公开(公告)号：US5047815A
公开(公告)日：1991-09-10
申请号：US394123
申请日：1989-08-14
申请人： Mitsuo Yasuhira , Takatoshi Yasui , Kazuhiro Matsuyama , Hideyuki Iwata , Masanori Fukumoto
发明人： Mitsuo Yasuhira , Takatoshi Yasui , Kazuhiro Matsuyama , Hideyuki Iwata , Masanori Fukumoto
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A semiconductor memory device includes a capacitor and an insulating separation area in a trench formed around a switching transistor, with a storage electrode of the capacitor being sandwiched between an upper and a lower cell plate electrode to reduce leakage current due to the parasitic MOS transistor effect in the trench sidewall along the channel in the switching transistor and leakage current due to the gate-controlled diode effect in the trench sidewall. Also, a method is disclosed for manufacturing such semiconductor memory device.
摘要翻译：半导体存储器件包括在开关晶体管周围形成的沟槽中的电容器和绝缘分离区域，电容器的存储电极夹在上和下单元电极板电极之间，以减少由寄生MOS晶体管效应引起的漏电流在开关晶体管中的通道的沟槽侧壁中，由于在沟槽侧壁中的栅极控制的二极管效应引起的漏电流。此外，公开了一种用于制造这种半导体存储器件的方法。

2. 发明申请

US20070008007A1 Input/output circuit device 有权
标题翻译：输入/输出电路设备
公开(公告)号：US20070008007A1
公开(公告)日：2007-01-11
申请号：US11436641
申请日：2006-05-19
申请人： Takatoshi Yasui
发明人： Takatoshi Yasui
IPC分类号： H03K19/094
CPC分类号： H03K19/018507 , H01L27/088 , H01L27/1203
摘要： An input/output circuit device includes a first transistor which is formed at a substrate, a first gate of which receives an input signal, one of a first source and drain of which is connected to a first power supply terminal, and the other of the first source and drain of which is connected to an internal node; and a second transistor which is formed at the substrate, a second gate of which is connected to a second power supply terminal, one of a second source and drain of which is connected to an input/output node, and the other of the second source and drain of which is connected to the internal node. The substrate of the second transistor has an electrically floating potential.
摘要翻译：输入/输出电路装置包括形成在基板上的第一晶体管，其第一栅极接收输入信号，第一晶体管的第一源极和漏极中的一个连接到第一电源端子，另一个其第一源和漏极连接到内部节点; 以及形成在所述基板上的第二晶体管，其第二栅极连接到第二电源端子，其第二源极和漏极中的一个连接到输入/输出节点，并且所述第二源极中的另一个源极其漏极连接到内部节点。第二晶体管的衬底具有电浮置电位。

3. 发明授权

US07042007B2 Semiconductor device and method for evaluating characteristics of the same 失效
标题翻译：用于评估其特性的半导体器件和方法
公开(公告)号：US07042007B2
公开(公告)日：2006-05-09
申请号：US10824426
申请日：2004-04-15
申请人： Takatoshi Yasui , Atsuhiro Kajiya
发明人： Takatoshi Yasui , Atsuhiro Kajiya
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , H01L27/088 , H01L2924/0002 , Y10S257/919 , H01L2924/00
摘要： A single evaluation portion is formed by disposing a plurality of MIS transistors used for evaluation having substantially the same structure as that of an actually used MIS transistor. In the evaluation portion, the respective source regions, drain regions, and gate electrodes of the MIS transistors used for evaluation are electrically connected in common to a source pad, a drain pad, and a gate pad, respectively. If the effective gate width of the single evaluation portion exceeds a given value, variations in characteristics evaluated by the evaluation portion approach variations in the characteristics of the entire semiconductor device. The accuracy of evaluating the characteristics of the semiconductor device can thus be improved by using the evaluation portion.
摘要翻译：单个评估部分通过设置用于评估的多个MIS晶体管形成，其具有与实际使用的MIS晶体管基本相同的结构。在评估部分中，用于评估的MIS晶体管的各个源极区域，漏极区域和栅极电极分别电连接到源极焊盘，漏极焊盘和栅极焊盘。如果单个评估部分的有效栅极宽度超过给定值，则由评估部分评估的特性的变化导致整个半导体器件的特性的变化。因此，可以通过使用评价部来提高评价半导体装置的特性的精度。

4. 发明申请

US20050161745A1 CMOS device, method for fabricating the same and method for generating mask data 审中-公开
标题翻译： CMOS器件，其制造方法以及用于生成掩模数据的方法
公开(公告)号：US20050161745A1
公开(公告)日：2005-07-28
申请号：US11028526
申请日：2005-01-05
申请人： Tokuhiko Tamaki , Hiromasa Fujimoto , Takatoshi Yasui , Takehiro Hirai
发明人： Tokuhiko Tamaki , Hiromasa Fujimoto , Takatoshi Yasui , Takehiro Hirai
IPC分类号： G03F1/20 , H01L21/266 , H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/76 , H01L31/062
CPC分类号： H01L21/823842
摘要： An NMIS gate implantation layer is generated by a method in which mask data of a P-type well implantation layer are added to mask data obtained by subtracting mask data of an NMIS-SD implantation layer and PMIS-SD implantation layer from mask data of an N-type well implantation layer. In a CMOS device fabricating process, ions are implanted into a polysilicon film by using the NMIS gate implantation layer, resulting in reduction in the total numbers of PN junctions and non-doped regions in a gate polysilicon film.
摘要翻译：通过将P型阱注入层的掩模数据添加到通过从掩模数据中减去NMIS-SD注入层和PMIS-SD注入层的掩模数据而获得的掩模数据的方法来产生NMIS栅极注入层 N型井注入层。在CMOS器件制造工艺中，通过使用NMIS栅极注入层将离子注入到多晶硅膜中，导致栅极多晶硅膜中PN结和非掺杂区域的总数减少。

5. 发明授权

US5786273A Semiconductor device and associated fabrication method 失效
标题翻译：半导体器件及相关制造方法
公开(公告)号：US5786273A
公开(公告)日：1998-07-28
申请号：US602575
申请日：1996-02-14
申请人： Toshitaka Hibi , Takatoshi Yasui , Hisashi Ogawa , Susumu Akamatsu , Shunsuke Kugo
发明人： Toshitaka Hibi , Takatoshi Yasui , Hisashi Ogawa , Susumu Akamatsu , Shunsuke Kugo
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/768
摘要： Formed in a second interlayer dielectric are a first contact hole and a second contact hole. The first and second contact holes each extend to a first-level interconnect line. Tungsten is formed on the entirety of a substrate to form a first plug, a second plug, and a tungsten layer. A silicon oxide layer is formed. Thereafter, a patterning process is carried out to form a second-level interconnect line which is connected with the first plug and a top protective layer, and the top of the second plug remains exposed. A sidewall is formed on the side surfaces of the second-level interconnect line and the top protective layer. Subsequently, a third-level interconnect line, which is connected with the exposed second plug, is formed. Such arrangement not only reduces the number of contact hole formation masks, it also cuts down the number of fabrication steps. Further, the aspect ratio of the second contact hole becomes lower thereby achieving highly reliable semiconductor devices.
摘要翻译：形成在第二层间电介质中的是第一接触孔和第二接触孔。第一和第二接触孔各自延伸到第一级互连线。在整个基板上形成钨以形成第一插塞，第二插头和钨层。形成氧化硅层。此后，进行图案化处理以形成与第一插头和顶部保护层连接的第二级互连线，并且第二插头的顶部保持暴露。侧壁形成在第二级互连线和顶部保护层的侧表面上。随后，形成与暴露的第二插头连接的第三级互连线。这种布置不仅减少了接触孔形成掩模的数量，而且还减少了制造步骤的数量。此外，第二接触孔的纵横比变低，从而实现高可靠性的半导体器件。

6. 发明授权

US07388401B2 Input/output circuit device 有权
标题翻译：输入/输出电路设备
公开(公告)号：US07388401B2
公开(公告)日：2008-06-17
申请号：US11436641
申请日：2006-05-19
申请人： Takatoshi Yasui
发明人： Takatoshi Yasui
IPC分类号： H03K19/173
CPC分类号： H03K19/018507 , H01L27/088 , H01L27/1203
摘要： An input/output circuit device includes a first transistor which is formed at a substrate, a first gate of which receives an input signal, one of a first source and drain of which is connected to a first power supply terminal, and the other of the first source and drain of which is connected to an internal node; and a second transistor which is formed at the substrate, a second gate of which is connected to a second power supply terminal, one of a second source and drain of which is connected to an input/output node, and the other of the second source and drain of which is connected to the internal node. The substrate of the second transistor has an electrically floating potential.
摘要翻译：输入/输出电路装置包括形成在基板上的第一晶体管，其第一栅极接收输入信号，第一晶体管的第一源极和漏极中的一个连接到第一电源端子，另一个其第一源和漏极连接到内部节点; 以及形成在所述基板上的第二晶体管，其第二栅极连接到第二电源端子，其第二源极和漏极中的一个连接到输入/输出节点，并且所述第二源极中的另一个源极其漏极连接到内部节点。第二晶体管的衬底具有电浮置电位。

7. 发明授权

US6110775A Process for fabrication of a dram cell having a stacked capacitor 失效
标题翻译：具有堆叠电容器的电容器的制造方法
公开(公告)号：US6110775A
公开(公告)日：2000-08-29
申请号：US18181
申请日：1998-02-03
申请人： Toyokazu Fujii , Takatoshi Yasui
发明人： Toyokazu Fujii , Takatoshi Yasui
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/20
CPC分类号： H01L28/82 , H01L28/91
摘要： A DRAM cell transistor formed on a silicon substrate comprises a first BPSG film, a silicon oxide film as a supporting film laid thereover, a storage node including a contact portion filling a contact hole extended through the silicon oxide film and the first BPSG film, an oxidized silicon nitride film as a capacitor insulating film, and a plate electrode. There may be further provided a second BPSG film thereover. Even if the first BPSG film at a lower level is caused to reflow by a process for oxidizing the silicon nitride film for formation of the oxidized silicon nitride film as the capacitor insulating film or a process for ref lowing the second BPSG film, the silicon oxide film as the supporting film applies to the capacitor insulating film a stress against the deformation thereof and hence, the oxidized silicon nitride film free from wrinkle or cracks is provided as the capacitor insulating film. Thus, a semiconductor device free from wrinkle or cracks in the nitride film associated with thermal history and a process for fabrication of the same can be offered, even though the nitride film is laid over the insulating film having a reflowable property.
摘要翻译：形成在硅衬底上的DRAM单元晶体管包括第一BPSG膜，作为其上放置的支撑膜的氧化硅膜，存储节点，包括填充延伸穿过氧化硅膜的接触孔和第一BPSG膜的接触部分，氧化氮化硅膜作为电容器绝缘膜，和平板电极。此外可以进一步提供第二BPSG膜。即使通过用于氧化氮化硅膜以形成作为电容器绝缘膜的氧化的氮化硅膜的工艺或降低第二BPSG膜的工艺，使较低级别的第一BPSG膜回流，则氧化硅作为支撑膜的膜作为电容绝缘膜，适用于电容器绝缘膜对其变形的应力，因此，作为电容器绝缘膜，提供没有褶皱或裂纹的氧化的氮化硅膜。因此，即使将氮化膜覆盖在具有可回流性的绝缘膜上，也可以提供与热历史相关的氮化物膜中没有皱纹或裂纹的半导体器件及其制造方法。

8. 发明授权

US5314848A Method for manufacturing a semiconductor device using a heat treatment according to a temperature profile that prevents grain or particle precipitation during reflow 失效
标题翻译：根据温度分布的热处理制造半导体器件的方法，该温度分布防止在回流期间晶粒或颗粒沉淀
公开(公告)号：US5314848A
公开(公告)日：1994-05-24
申请号：US764846
申请日：1991-09-24
申请人： Takatoshi Yasui , Chiaki Kudo , Ichiro Nakao , Toyokazu Fujii , Yuka Terai , Shinichi Imai , Hiroshi Yamamoto , Yasushi Naito
发明人： Takatoshi Yasui , Chiaki Kudo , Ichiro Nakao , Toyokazu Fujii , Yuka Terai , Shinichi Imai , Hiroshi Yamamoto , Yasushi Naito
IPC分类号： H01L21/3105 , H01L21/768 , H01L21/00 , H01L21/02 , H01L21/324 , H01L21/477
CPC分类号： H01L21/76819 , H01L21/3105 , Y10S148/133 , Y10S438/909
摘要： Described is a method for manufacturing semiconductor devices which includes a heat treating process for heating and cooling semiconductor substrates mounted on a boat at a predetermined pitch according to a predetermined temperature profile, in order to flatten the surface of each semiconductor substrate by reflowing an insulating film containing impurities, for example, a BPSG film formed on the substrate. In the heat treating process, one of the control factors which affects the formation of grains or particles due to the impurities contained in the insulating film is set so as to prevent the impurities from generating grains or particles during the heat treatment. Also disclosed is a method of preventing the generation of grains or particles by widening the pitch of the mounted substrates.
摘要翻译：描述了一种用于制造半导体器件的方法，其包括根据预定温度分布以预定间距对安装在船上的半导体衬底进行加热和冷却的热处理工艺，以便通过回流绝缘膜来平坦化每个半导体衬底的表面含有杂质，例如在基板上形成的BPSG膜。在热处理过程中，设定影响绝缘膜中含有杂质的晶粒或颗粒形成的控制因素之一，以防止杂质在热处理过程中产生晶粒或颗粒。还公开了通过扩大安装的基板的间距来防止颗粒或颗粒的产生的方法。

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