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1. 发明授权

US06187688B1 Pattern formation method 失效
标题翻译：图案形成方法
公开(公告)号：US06187688B1
公开(公告)日：2001-02-13
申请号：US09142252
申请日：1998-09-18
申请人： Mitsuhiro Ohkuni , Shunsuke Kugo , Tomoyuki Sasaki , Kenji Tateiwa , Hideo Nikoh
发明人： Mitsuhiro Ohkuni , Shunsuke Kugo , Tomoyuki Sasaki , Kenji Tateiwa , Hideo Nikoh
IPC分类号： H01L2100
CPC分类号： G03F7/091 , H01L21/31138 , H01L21/32139
摘要： After an organic bottom anti-reflective coating (12) is deposited on an underlying film (11), a resist pattern (15) is formed on the organic bottom anti-reflective coating (12). Dry etching is performed with respect to the organic bottom anti-reflective coating (12) masked with the resist pattern (15) to form an anti-reflective coating pattern. The dry-etching of the organic bottom anti-reflective coating (12) is performed by using etching gas containing gas having the S component such as SO2/O2-based etching gas or COS/O2-based etching gas.
摘要翻译：在有机底部抗反射涂层（12）沉积在下面的膜（11）上之后，在有机底部抗反射涂层（12）上形成抗蚀剂图案（15）。相对于用抗蚀剂图案（15）掩蔽的有机底部防反射涂层（12）进行干蚀刻以形成抗反射涂层图案。有机底部防反射涂层（12）的干蚀刻是通过使用含有S成分的气体的蚀刻气体，例如基于SO 2 / O 2的蚀刻气体或COS / O2系蚀刻气体进行的。

2. 发明授权

US6007673A Apparatus and method of producing an electronic device 失效
标题翻译：电子设备的制造方法及装置
公开(公告)号：US6007673A
公开(公告)日：1999-12-28
申请号：US942441
申请日：1997-10-01
申请人： Shunsuke Kugo , Hideo Nikoh , Tomoyuki Sasaki , Hideo Ichimura , Daihei Kajiwara , Shoji Matsumoto , Satoshi Nakagawa
发明人： Shunsuke Kugo , Hideo Nikoh , Tomoyuki Sasaki , Hideo Ichimura , Daihei Kajiwara , Shoji Matsumoto , Satoshi Nakagawa
IPC分类号： H01J37/32 , H01L21/3065 , H01L21/311 , B44C1/22 , H01L21/00
CPC分类号： H01J37/32458 , H01J37/321 , H01L21/3065 , H01L21/31116 , H01J2237/022 , Y10S156/916
摘要： A semiconductor substrate which is placed on a bottom electrode inside a chamber is dry-etched by creating plasma inside the chamber. By making the average surface roughness Ra of the bottom surface of a quartz-top plate placed on the bottom electrode be in a range of 0.2 to 5 .mu.m, adhesion between the quartz-top plate and the deposits caused by the dry etching is enhanced, and the number of particles suspended in the chamber is reduced. Furthermore, the function of enhancing the adhesion of deposits can be maintained even after cleaning of the quartz-top plate. As a result, the number of particles which adhere onto the semiconductor substrate is reduced and the semiconductor substrate can be processed in an extremely clean atmosphere.
摘要翻译：通过在腔室内产生等离子体，将放置在室内的底部电极上的半导体衬底进行干蚀刻。通过使放置在底部电极上的石英板的底面的平均表面粗糙度Ra在0.2〜5μm的范围内，石英板与由干蚀刻引起的沉积物之间的粘附性增强，并且悬浮在室中的颗粒数量减少。此外，即使在清洁石英板之后，也可以保持增加沉积物的附着力的功能。结果，粘附到半导体衬底上的颗粒数量减少，半导体衬底可以在非常干净的气氛中进行处理。

3. 发明授权

US06524904B1 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06524904B1
公开(公告)日：2003-02-25
申请号：US09551542
申请日：2000-04-18
申请人： Mizuki Segawa , Masatoshi Arai , Toshiki Yabu , Shunsuke Kugo
发明人： Mizuki Segawa , Masatoshi Arai , Toshiki Yabu , Shunsuke Kugo
IPC分类号： H01L218238
CPC分类号： H01L21/823842
摘要： After P+ ions are implanted into a polysilicon film in an nMOSFET region, a heat treatment is performed to diffuse phosphorus down to the lower part of the polysilicon film. The diffusion reduces the concentration of phosphorus in an upper end portion of the polysilicon film and inhibits the upper end edges of a gate electrode from being increased in size during patterning. Then, B+ ions are implanted into the polysilicon film in a pMOSFET region and the polysilicon film is etched into a gate configuration. Since a heat treatment for simultaneously diffusing phosphorus and boron in the polysilicon film is not performed, the entrance of boron from the gate electrode into a semiconductor substrate is inhibited, while the occurrence of side etching during the formation of an n-type polysilicon gate is suppressed.
摘要翻译：将P +离子注入nMOSFET区域中的多晶硅膜之后，进行热处理以将磷扩散到多晶硅膜的下部。扩散减少了多晶硅膜的上端部分中的磷的浓度，并且在图案化期间抑制栅电极的上端边缘的尺寸增大。然后，在pMOSFET区域中将B +离子注入到多晶硅膜中，并且将多晶硅膜蚀刻成栅极配置。由于不进行同时扩散多晶硅膜中的磷和硼的热处理，可以抑制从栅极引入到半导体衬底中的硼，同时在形成n型多晶硅栅极时发生侧蚀刻是被压制

4. 发明授权

US5786273A Semiconductor device and associated fabrication method 失效
标题翻译：半导体器件及相关制造方法
公开(公告)号：US5786273A
公开(公告)日：1998-07-28
申请号：US602575
申请日：1996-02-14
申请人： Toshitaka Hibi , Takatoshi Yasui , Hisashi Ogawa , Susumu Akamatsu , Shunsuke Kugo
发明人： Toshitaka Hibi , Takatoshi Yasui , Hisashi Ogawa , Susumu Akamatsu , Shunsuke Kugo
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/768
摘要： Formed in a second interlayer dielectric are a first contact hole and a second contact hole. The first and second contact holes each extend to a first-level interconnect line. Tungsten is formed on the entirety of a substrate to form a first plug, a second plug, and a tungsten layer. A silicon oxide layer is formed. Thereafter, a patterning process is carried out to form a second-level interconnect line which is connected with the first plug and a top protective layer, and the top of the second plug remains exposed. A sidewall is formed on the side surfaces of the second-level interconnect line and the top protective layer. Subsequently, a third-level interconnect line, which is connected with the exposed second plug, is formed. Such arrangement not only reduces the number of contact hole formation masks, it also cuts down the number of fabrication steps. Further, the aspect ratio of the second contact hole becomes lower thereby achieving highly reliable semiconductor devices.
摘要翻译：形成在第二层间电介质中的是第一接触孔和第二接触孔。第一和第二接触孔各自延伸到第一级互连线。在整个基板上形成钨以形成第一插塞，第二插头和钨层。形成氧化硅层。此后，进行图案化处理以形成与第一插头和顶部保护层连接的第二级互连线，并且第二插头的顶部保持暴露。侧壁形成在第二级互连线和顶部保护层的侧表面上。随后，形成与暴露的第二插头连接的第三级互连线。这种布置不仅减少了接触孔形成掩模的数量，而且还减少了制造步骤的数量。此外，第二接触孔的纵横比变低，从而实现高可靠性的半导体器件。

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