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1. 发明授权

US6007673A Apparatus and method of producing an electronic device 失效
标题翻译：电子设备的制造方法及装置
公开(公告)号：US6007673A
公开(公告)日：1999-12-28
申请号：US942441
申请日：1997-10-01
申请人： Shunsuke Kugo , Hideo Nikoh , Tomoyuki Sasaki , Hideo Ichimura , Daihei Kajiwara , Shoji Matsumoto , Satoshi Nakagawa
发明人： Shunsuke Kugo , Hideo Nikoh , Tomoyuki Sasaki , Hideo Ichimura , Daihei Kajiwara , Shoji Matsumoto , Satoshi Nakagawa
IPC分类号： H01J37/32 , H01L21/3065 , H01L21/311 , B44C1/22 , H01L21/00
CPC分类号： H01J37/32458 , H01J37/321 , H01L21/3065 , H01L21/31116 , H01J2237/022 , Y10S156/916
摘要： A semiconductor substrate which is placed on a bottom electrode inside a chamber is dry-etched by creating plasma inside the chamber. By making the average surface roughness Ra of the bottom surface of a quartz-top plate placed on the bottom electrode be in a range of 0.2 to 5 .mu.m, adhesion between the quartz-top plate and the deposits caused by the dry etching is enhanced, and the number of particles suspended in the chamber is reduced. Furthermore, the function of enhancing the adhesion of deposits can be maintained even after cleaning of the quartz-top plate. As a result, the number of particles which adhere onto the semiconductor substrate is reduced and the semiconductor substrate can be processed in an extremely clean atmosphere.
摘要翻译：通过在腔室内产生等离子体，将放置在室内的底部电极上的半导体衬底进行干蚀刻。通过使放置在底部电极上的石英板的底面的平均表面粗糙度Ra在0.2〜5μm的范围内，石英板与由干蚀刻引起的沉积物之间的粘附性增强，并且悬浮在室中的颗粒数量减少。此外，即使在清洁石英板之后，也可以保持增加沉积物的附着力的功能。结果，粘附到半导体衬底上的颗粒数量减少，半导体衬底可以在非常干净的气氛中进行处理。

2. 发明授权

US06187688B1 Pattern formation method 失效
标题翻译：图案形成方法
公开(公告)号：US06187688B1
公开(公告)日：2001-02-13
申请号：US09142252
申请日：1998-09-18
申请人： Mitsuhiro Ohkuni , Shunsuke Kugo , Tomoyuki Sasaki , Kenji Tateiwa , Hideo Nikoh
发明人： Mitsuhiro Ohkuni , Shunsuke Kugo , Tomoyuki Sasaki , Kenji Tateiwa , Hideo Nikoh
IPC分类号： H01L2100
CPC分类号： G03F7/091 , H01L21/31138 , H01L21/32139
摘要： After an organic bottom anti-reflective coating (12) is deposited on an underlying film (11), a resist pattern (15) is formed on the organic bottom anti-reflective coating (12). Dry etching is performed with respect to the organic bottom anti-reflective coating (12) masked with the resist pattern (15) to form an anti-reflective coating pattern. The dry-etching of the organic bottom anti-reflective coating (12) is performed by using etching gas containing gas having the S component such as SO2/O2-based etching gas or COS/O2-based etching gas.
摘要翻译：在有机底部抗反射涂层（12）沉积在下面的膜（11）上之后，在有机底部抗反射涂层（12）上形成抗蚀剂图案（15）。相对于用抗蚀剂图案（15）掩蔽的有机底部防反射涂层（12）进行干蚀刻以形成抗反射涂层图案。有机底部防反射涂层（12）的干蚀刻是通过使用含有S成分的气体的蚀刻气体，例如基于SO 2 / O 2的蚀刻气体或COS / O2系蚀刻气体进行的。

3. 发明授权

US5989929A Apparatus and method for manufacturing semiconductor device 失效
标题翻译：半导体器件制造装置及方法
公开(公告)号：US5989929A
公开(公告)日：1999-11-23
申请号：US119588
申请日：1998-07-21
申请人： Hideo Nikoh , Shinichi Imai , Nobuhiro Jiwari , Satoshi Nakagawa , Shoji Matsumoto , Yoji Bito
发明人： Hideo Nikoh , Shinichi Imai , Nobuhiro Jiwari , Satoshi Nakagawa , Shoji Matsumoto , Yoji Bito
IPC分类号： H01J37/32 , H01L21/00
CPC分类号： H01L21/67253 , H01J37/321 , H01J37/32422 , H01J37/32467 , H01J37/32871 , H01J37/3299 , H01L21/67069 , H01L21/67248
摘要： A reactor is composed of a lower frame of a chamber, a quartz dome, an upper electrode, an 0 ring, and the like. A lower electrode and a substrate as a workpiece to be processed thereon are disposed in the reactor. The temperature of the quartz dome is maintained at a temperature of 180.degree. C. or higher by means of a heater. Fluorocarbon gas such as C.sub.2 F.sub.6 gas or C.sub.4 F.sub.8 gas is introduced into the reactor through a gas inlet and RF power from a first RF power source is applied to an antenna coil to produce a plasma and thereby etch an oxide film on the substrate. By heating the quartz dome to a high temperature, a deposit which hinders the release of oxygen from a wall face is prevented from being attached and the deposit on the bottom of the hole which causes an etch stop during processing is removed with oxygen. This prevents the etch stop during an etching process for forming a deep hole.
摘要翻译：反应器由室的下框架，石英圆顶，上电极，O形环等构成。作为待加工的工件的下电极和基板设置在反应器中。通过加热器将石英圆顶的温度保持在180℃或更高的温度。将碳氟化合物气体如C 2 F 6气体或C 4 F 8气体通过气体入口引入反应器中，并且将来自第一RF电源的RF功率施加到天线线圈以产生等离子体，从而蚀刻衬底上的氧化物膜。通过将石英圆顶加热到高温，防止阻碍氧从壁面释放的沉积物被附着，并且用氧气除去在加工过程中导致蚀刻停止的孔的沉积物。这防止了在用于形成深孔的蚀刻工艺期间的蚀刻停止。

4. 发明授权

US06960531B2 Method of manufacturing electronic device 失效
标题翻译：制造电子装置的方法
公开(公告)号：US06960531B2
公开(公告)日：2005-11-01
申请号：US10819968
申请日：2004-04-08
申请人： Tomoyuki Sasaki , Takao Yamaguchi , Hideo Nikoh
发明人： Tomoyuki Sasaki , Takao Yamaguchi , Hideo Nikoh
IPC分类号： H01L21/28 , H01L21/308 , H01L21/311 , H01L21/3213 , H01L21/302 , B08B6/00 , H01L21/461
CPC分类号： H01L21/0206 , H01L21/02063 , H01L21/28123 , H01L21/3081 , H01L21/3086 , H01L21/31116 , H01L21/31144 , H01L21/32137 , H01L21/32139 , H01L21/76802 , H01L21/76807 , H01L21/76814 , H01L21/76838
摘要： After forming an insulating film on an underlying layer, a resist pattern is formed on the insulating film. The insulating film is etched by using the resist pattern as a mask, thereby forming an insulating film pattern. Without removing the resist pattern, exposed portions of the underlying layer and the insulating film pattern are subjected to a plasma treatment, cleaning, a heat treatment or the like, so that a deposition grown during the formation of the insulating film pattern can be removed. Thereafter, the underlying layer is etched by using at least the insulating film pattern as a mask. As a result, even when a strict pattern rule is employed, pattern defects can be prevented from being caused in etching a multi-layer film.
摘要翻译：在下层形成绝缘膜之后，在绝缘膜上形成抗蚀剂图案。通过使用抗蚀剂图案作为掩模来蚀刻绝缘膜，由此形成绝缘膜图案。在不去除抗蚀剂图案的情况下，对下面的层和绝缘膜图案的暴露部分进行等离子体处理，清洁，热处理等，从而可以去除在形成绝缘膜图案期间生长的沉积。此后，使用至少绝缘膜图案作为掩模来蚀刻下层。结果，即使采用严格的图案规则，也可以防止在蚀刻多层膜时引起图案缺陷。

5. 发明授权

US06750149B2 Method of manufacturing electronic device 有权
标题翻译：制造电子装置的方法
公开(公告)号：US06750149B2
公开(公告)日：2004-06-15
申请号：US10043257
申请日：2002-01-14
申请人： Tomoyuki Sasaki , Takao Yamaguchi , Hideo Nikoh
发明人： Tomoyuki Sasaki , Takao Yamaguchi , Hideo Nikoh
IPC分类号： H01L21302
CPC分类号： H01L21/0206 , H01L21/02063 , H01L21/28123 , H01L21/3081 , H01L21/3086 , H01L21/31116 , H01L21/31144 , H01L21/32137 , H01L21/32139 , H01L21/76802 , H01L21/76807 , H01L21/76814 , H01L21/76838
摘要： After forming an insulating film on an underlying layer, a resist pattern is formed on the insulating film. The insulating film is etched by using the resist pattern as a mask, thereby forming an insulating film pattern. Without removing the resist pattern, exposed portions of the underlying layer and the insulating film pattern are subjected to a plasma treatment, cleaning, a heat treatment or the like, so that a deposition grown during the formation of the insulating film pattern can be removed. Thereafter, the underlying layer is etched by using at least the insulating film pattern as a mask. As a result, even when a strict pattern rule is employed, pattern defects can be prevented from being caused in etching a multi-layer film.
摘要翻译：在下层形成绝缘膜之后，在绝缘膜上形成抗蚀剂图案。通过使用抗蚀剂图案作为掩模来蚀刻绝缘膜，由此形成绝缘膜图案。在不去除抗蚀剂图案的情况下，对下面的层和绝缘膜图案的暴露部分进行等离子体处理，清洁，热处理等，从而可以去除在形成绝缘膜图案期间生长的沉积。此后，使用至少绝缘膜图案作为掩模来蚀刻下层。结果，即使采用严格的图案规则，也可以防止在蚀刻多层膜时引起图案缺陷。

6. 发明申请

US20060003575A1 Method of manufacturing electronic device 审中-公开
公开(公告)号：US20060003575A1
公开(公告)日：2006-01-05
申请号：US11189900
申请日：2005-07-27
申请人： Tomoyuki Sasaki , Takao Yamaguchi , Hideo Nikoh
发明人： Tomoyuki Sasaki , Takao Yamaguchi , Hideo Nikoh
IPC分类号： H01L21/4763
CPC分类号： H01L21/0206 , H01L21/02063 , H01L21/28123 , H01L21/3081 , H01L21/3086 , H01L21/31116 , H01L21/31144 , H01L21/32137 , H01L21/32139 , H01L21/76802 , H01L21/76807 , H01L21/76814 , H01L21/76838
摘要： After forming an insulating film on an underlying layer, a resist pattern is formed on the insulating film. The insulating film is etched by using the resist pattern as a mask, thereby forming an insulating film pattern. Without removing the resist pattern, exposed portions of the underlying layer and the insulating film pattern are subjected to a plasma treatment, cleaning, a heat treatment or the like, so that a deposition grown during the formation of the insulating film pattern can be removed. Thereafter, the underlying layer is etched by using at least the insulating film pattern as a mask. As a result, even when a strict pattern rule is employed, pattern defects can be prevented from being caused in etching a multi-layer film.

7. 发明授权

US06214740B1 Semiconductor manufacturing apparatus 失效
标题翻译：半导体制造装置
公开(公告)号：US06214740B1
公开(公告)日：2001-04-10
申请号：US09051815
申请日：1998-04-16
申请人： Shinichi Imai , Hideo Nikoh , Nobuhiro Jiwari
发明人： Shinichi Imai , Hideo Nikoh , Nobuhiro Jiwari
IPC分类号： H01L21461
CPC分类号： H01L21/67069 , H01L21/3065
摘要： A manufacturing apparatus for semiconductor devices comprises as a halogen scavenger a silicon ring (12) having an average surface roughness of 1-1000 &mgr;m, arranged around a silicon substrate (6) on a lower electrode (3) in a reaction chamber (7); and an upper silicon element (5) as another halogen scavenger, having an average surface roughness of 1-1000 &mgr;m, arranged above the silicon substrate (6). In this apparatus, C2F6 is used as a gas to be introduced into the chamber (7) and fluorine can be effectively scavenged in the initial phase of operation, so that semiconductor devices can be aged faster than in conventional apparatus.
摘要翻译：半导体器件的制造装置包括作为卤素清除剂的平均表面粗糙度为1-1000μm的硅环（12），其布置在反应室（7）中的下电极（3）上的硅衬底（6）周围， ; 和作为另一个卤素清除剂的上硅元件（5），其平均表面粗糙度为1-1000μm，设置在硅衬底（6）的上方。在该装置中，C2F6用作被引入到室（7）中的气体，并且在初始操作阶段可以有效地清除氟，使得半导体器件的老化速度可以比传统的设备快。

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