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1. 发明申请

US20120021605A1 SEMICONDUCTOR DEVICE PRODUCING METHOD 有权
标题翻译：半导体器件生产方法
公开(公告)号：US20120021605A1
公开(公告)日：2012-01-26
申请号：US13013380
申请日：2011-01-25
申请人： Mitsuhiro OMURA , Yumi Ohno , Takaya Matsushita , Tokuhisa Ohiwa
发明人： Mitsuhiro OMURA , Yumi Ohno , Takaya Matsushita , Tokuhisa Ohiwa
IPC分类号： H01L21/475 , H01L21/4757
CPC分类号： H01L21/31116 , H01L21/0273 , H01L21/31144 , H01L21/32139
摘要： In a semiconductor device producing method according to one embodiment, an insulating film containing silicon is formed on a semiconductor substrate, a resist is deposited on the insulating film, the resist is patterned into a predetermined pattern, and the insulating film is processed by a dry etching treatment in which gas containing C, F, Br, H, and O is used with the resist having the predetermined pattern as a mask. A deposited film in which C and Br are coupled is produced on the resist.
摘要翻译：在根据一个实施例的半导体器件制造方法中，在半导体衬底上形成含有硅的绝缘膜，在绝缘膜上沉积抗蚀剂，将抗蚀剂图案化成预定图案，并且通过干燥蚀刻处理，其中使用含有C，F，Br，H和O的气体，其中具有预定图案的抗蚀剂作为掩模。在抗蚀剂上制造其中C和Br连接的沉积膜。

2. 发明授权

US08513134B2 Semiconductor device producing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08513134B2
公开(公告)日：2013-08-20
申请号：US13013380
申请日：2011-01-25
申请人： Mitsuhiro Omura , Yumi Ohno , Takaya Matsushita , Tokuhisa Ohiwa
发明人： Mitsuhiro Omura , Yumi Ohno , Takaya Matsushita , Tokuhisa Ohiwa
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/0273 , H01L21/31144 , H01L21/32139
摘要： In a semiconductor device producing method according to one embodiment, an insulating film containing silicon is formed on a semiconductor substrate, a resist is deposited on the insulating film, the resist is patterned into a predetermined pattern, and the insulating film is processed by a dry etching treatment in which gas containing C, F, Br, H, and O is used with the resist having the predetermined pattern as a mask. A deposited film in which C and Br are coupled is produced on the resist.
摘要翻译：在根据一个实施例的半导体器件制造方法中，在半导体衬底上形成含有硅的绝缘膜，在绝缘膜上沉积抗蚀剂，将抗蚀剂图案化成预定图案，并且通过干燥蚀刻处理，其中使用含有C，F，Br，H和O的气体，其中具有预定图案的抗蚀剂作为掩模。在抗蚀剂上制造其中C和Br连接的沉积膜。

3. 发明授权

US5310454A Dry etching method 失效
标题翻译：干蚀刻法
公开(公告)号：US5310454A
公开(公告)日：1994-05-10
申请号：US26042
申请日：1993-03-04
申请人： Tokuhisa Ohiwa , Hisataka Hayashi , Keiji Horioka , Haruo Okano , Takaya Matsushita , Isahiro Hasegawa , Akira Takeuchi
发明人： Tokuhisa Ohiwa , Hisataka Hayashi , Keiji Horioka , Haruo Okano , Takaya Matsushita , Isahiro Hasegawa , Akira Takeuchi
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/31116
摘要： A dry etching method by a plasma etching forms a mask pattern, having an opening up to 1 .mu.m width on a silicon oxide layer formed on a silicon substrate. The substrate is laced into a reactive chamber having an etching gas introducing means and fluorocarbon gas and hydrogen gas as the etching gas are introduced such that a ratio of the hydrogen gas to the gas mixture satisfies 50% to 80%. The plasma is generated, and by using the plasma etching, the silicon oxide layer is etched according to the mask pattern to form an opening having an aspect ratio of more than 1 in the silicon oxide layer.
摘要翻译：通过等离子体蚀刻的干蚀刻方法形成在硅基板上形成的氧化硅层上具有至多1μm宽的开口的掩模图案。衬底被引入具有蚀刻气体引入装置的反应室和碳氟化合物气体和氢气作为蚀刻气体，使得氢气与气体混合物的比率满足50％至80％。产生等离子体，并且通过使用等离子体蚀刻，根据掩模图案蚀刻氧化硅层，以在氧化硅层中形成长径比大于1的开口。

4. 发明授权

US07232763B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07232763B2
公开(公告)日：2007-06-19
申请号：US10959501
申请日：2004-10-07
申请人： Mitsuhiro Omura , Makiko Katano , Shoko Ito , Takaya Matsushita , Hisashi Kaneko
发明人： Mitsuhiro Omura , Makiko Katano , Shoko Ito , Takaya Matsushita , Hisashi Kaneko
IPC分类号： H01L21/311
CPC分类号： H01L21/76838 , H01L21/02046 , H01L21/31116
摘要： A method of manufacturing a semiconductor device includes subjecting a semiconductor wafer, which includes a copper layer formed above a semiconductor substrate and covered with an insulating film, to a dry etching using a fluorocarbon gas to partially remove the insulating film, thereby at least partially exposing a surface of the copper layer. The copper layer, the surface of which is at least partially exposed is subjected to a nitrogen plasma treatment. The semiconductor wafer having the nitrogen plasma-treated copper layer is exposed to atmosphere, and then the semiconductor wafer is subjected to a surface treatment.
摘要翻译：一种制造半导体器件的方法包括使用碳氟化合物气体对包含形成在半导体衬底之上并被绝缘膜形成的铜层的半导体晶片进行干蚀刻，以部分地去除绝缘膜，从而至少部分曝光铜层的表面。将其表面至少部分暴露的铜层进行氮等离子体处理。将具有氮等离子体处理的铜层的半导体晶片暴露于大气中，然后对半导体晶片进行表面处理。

5. 发明申请

US20050106866A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050106866A1
公开(公告)日：2005-05-19
申请号：US10959501
申请日：2004-10-07
申请人： Mitsuhiro Omura , Makiko Katano , Shoko Ito , Takaya Matsushita , Hisashi Kaneko
发明人： Mitsuhiro Omura , Makiko Katano , Shoko Ito , Takaya Matsushita , Hisashi Kaneko
IPC分类号： H01L21/00 , H01L21/26 , H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/311 , H01L21/324 , H01L21/44 , H01L21/461 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76838 , H01L21/02046 , H01L21/31116
摘要： A method of manufacturing a semiconductor device includes subjecting a semiconductor wafer, which includes a copper layer formed above a semiconductor substrate and covered with an insulating film, to a dry etching using a fluorocarbon gas to partially remove the insulating film, thereby at least partially exposing a surface of the copper layer. The copper layer, the surface of which is at least partially exposed is subjected to a nitrogen plasma treatment. The semiconductor wafer having the nitrogen plasma-treated copper layer is exposed to atmosphere, and then the semiconductor wafer is subjected to a surface treatment.
摘要翻译：一种制造半导体器件的方法包括使用碳氟化合物气体对包含形成在半导体衬底之上并被绝缘膜形成的铜层的半导体晶片进行干蚀刻，以部分地去除绝缘膜，从而至少部分曝光铜层的表面。将其表面至少部分暴露的铜层进行氮等离子体处理。将具有氮等离子体处理的铜层的半导体晶片暴露于大气中，然后对半导体晶片进行表面处理。

6. 发明授权

US07943459B2 Semiconductor device and method of manufacturing the semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07943459B2
公开(公告)日：2011-05-17
申请号：US11892635
申请日：2007-08-24
申请人： Kazutaka Akiyama , Takaya Matsushita
发明人： Kazutaka Akiyama , Takaya Matsushita
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/425
CPC分类号： H01L23/5258 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided with a conductor wire and a fuse wire formed in an insulating film over a semiconductor substrate, a first under-pad-wire insulating film formed above the insulating film, a second under-pad-wire insulating film formed on the first under-pad-wire insulating film, a pad wire formed in an area above the conductive wire, in the first and second under-pad-wire insulating films and an opening formed by leaving a part of the first under-pad-wire insulating film in an area above the fuse wire, in the first and second under-pad-wire insulating films, wherein the second under-pad-wire insulating film comprises an element different from that of the first under-pad-wire insulating film.
摘要翻译：半导体器件设置有形成在半导体衬底上的绝缘膜中的导体线和熔丝，在绝缘膜上方形成的第一焊盘下绝缘膜，形成在绝缘膜上的第二焊盘下绝缘膜第一下焊丝线绝缘膜，形成在导电线上方的区域中的焊盘，位于第一和第二焊盘下绝缘膜中的开口，以及通过留下第一下焊丝线绝缘的一部分而形成的开口在第一和第二下焊丝线绝缘膜中的熔丝线上方的区域中的第二底焊丝线绝缘膜，其中第二焊盘下绝缘膜包括与第一焊盘下绝缘膜不同的元件。

7. 发明授权

US5271788A Plasma processing apparatus 失效
标题翻译：等离子体处理装置
公开(公告)号：US5271788A
公开(公告)日：1993-12-21
申请号：US917361
申请日：1992-07-23
申请人： Makoto Hasegawa , Takaya Matsushita , Keiji Horioka , Isahiro Hasegawa , Toshihisa Nozawa , Yoshio Ishikawa , Masahito Hiratsuka , Satoshi Kaneko
发明人： Makoto Hasegawa , Takaya Matsushita , Keiji Horioka , Isahiro Hasegawa , Toshihisa Nozawa , Yoshio Ishikawa , Masahito Hiratsuka , Satoshi Kaneko
IPC分类号： H01J37/32 , C23F1/02
CPC分类号： H01J37/32082 , H01J37/3255 , H01J37/32623 , H01J37/32642 , H01J37/3266
摘要： A magnetron plasma etching apparatus comprises a suscepter serving as an electrode on which a silicon wafer is mounted. A carbon ring having an outer diameter larger than the diameter of the wafer and an electrical resistance lower than that of the wafer, is arranged around the suscepter. The carbon ring is electrically connected to the suscepter. The carbon ring improves uniformity of etching of the wafer.

8. 发明授权

US06627557B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06627557B2
公开(公告)日：2003-09-30
申请号：US09819770
申请日：2001-03-29
申请人： Shoji Seta , Takaya Matsushita
发明人： Shoji Seta , Takaya Matsushita
IPC分类号： H01L21302
CPC分类号： H01L21/76816 , H01L21/28123 , H01L21/3081 , H01L21/31144 , H01L21/32139 , H01L21/76807 , H01L21/76811 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of manufacturing a semiconductor device, which comprises the steps of forming an insulating film or a metal film on a surface of a semiconductor substrate, forming at least two kinds of mask on a surface of the insulating film or the metal film, and performing a plurality of etching works to the insulating film or the metal film in conformity with the various kinds of mask.
摘要翻译：公开了一种制造半导体器件的方法，其包括在半导体衬底的表面上形成绝缘膜或金属膜的步骤，在绝缘膜或金属膜的表面上形成至少两种掩模，以及根据各种掩模对绝缘膜或金属膜进行多次蚀刻工作。

9. 发明授权

US5595627A Plasma etching method 失效
标题翻译：等离子蚀刻法
公开(公告)号：US5595627A
公开(公告)日：1997-01-21
申请号：US597563
申请日：1996-02-02
申请人： Koichiro Inazawa , Shin Okamoto , Hisataka Hayashi , Takaya Matsushita
发明人： Koichiro Inazawa , Shin Okamoto , Hisataka Hayashi , Takaya Matsushita
IPC分类号： H05H1/46 , C23F4/00 , C30B33/12 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/00 , C09K13/00
CPC分类号： H01L21/31116
摘要： A plasma etching apparatus has a lower electrode for supporting a semiconductor wafer in a processing room, an upper electrode opposite to the lower electrode, and an RF power supply for applying an RF power across the upper and lower electrodes. An SiN layer as an underlayer having a shoulder portion, and an SiO.sub.2 layer covering the SiN layer are disposed on the wafer. A contact hole is formed in the SiO.sub.2 layer by etching so as to expose the shoulder portion of the SiN layer. A processing gas contains C.sub.4 F.sub.8 and CO. To set the etching selection ratio of SiO.sub.2 /SiN, the discharge duration of each part of the processing gas is used as a parameter. The progress of dissociation of C.sub.4 F.sub.8 is controlled by selecting the discharge duration. The discharge duration is determined by the residence time of each part of the processing gas and the application time of an RF power.
摘要翻译：等离子体蚀刻装置具有用于在处理室中支撑半导体晶片的下电极，与下电极相对的上电极，以及用于在上电极和下电极上施加RF电力的RF电源。作为具有肩部的底层的SiN层和覆盖SiN层的SiO 2层设置在晶片上。通过蚀刻在SiO 2层中形成接触孔，以露出SiN层的肩部。处理气体含有C4F8和CO。为了设定SiO 2 / SiN的蚀刻选择比，使用处理气体的各部分的排出持续时间作为参数。通过选择放电持续时间控制C4F8的离解进程。放电持续时间由处理气体的每个部分的停留时间和RF功率的施加时间决定。

10. 发明申请

US20110147942A1 METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：制造半导体存储器件和半导体存储器件的方法
公开(公告)号：US20110147942A1
公开(公告)日：2011-06-23
申请号：US12838960
申请日：2010-07-19
申请人： Katsunori YAHASHI , Takuji Kuniya , Takaya Matsushita , Murato Kawai , Shuichi Taniguchi
发明人： Katsunori YAHASHI , Takuji Kuniya , Takaya Matsushita , Murato Kawai , Shuichi Taniguchi
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L27/0688 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： A method of manufacturing a semiconductor memory device of an embodiment includes: after forming a first interconnection layer and a memory cell layer above a semiconductor substrate, forming first lines by forming first grooves extending in first direction; forming a thin film on the side walls of the first grooves; forming a stack structure by filling an interlayer insulating film in the first grooves; forming a second interconnection layer above the stack structure; forming second lines by forming second grooves extending in second direction; removing the thin film exposed at bottom of the second grooves; and forming columnar memory cells by removing the memory cell layer exposed at bottom of the second grooves. The thin film has higher etching rate than the interlayer insulating film, and is removed prior to portions of the memory cell layer adjoining the thin film.
摘要翻译：制造实施例的半导体存储器件的方法包括：在半导体衬底之上形成第一互连层和存储单元层之后，通过形成沿第一方向延伸的第一沟槽来形成第一线; 在第一槽的侧壁上形成薄膜; 通过在第一槽中填充层间绝缘膜形成堆叠结构; 在所述堆叠结构之上形成第二互连层; 通过形成沿第二方向延伸的第二凹槽形成第二线; 去除在第二凹槽的底部暴露的薄膜; 以及通过去除在第二凹槽的底部暴露的存储单元层来形成柱状存储单元。薄膜具有比层间绝缘膜更高的蚀刻速率，并且在与薄膜邻接的存储单元层的部分之前被去除。

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