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1. 发明授权

US5850268A Parallel processor apparatus 失效
标题翻译：并行处理器设备
公开(公告)号：US5850268A
公开(公告)日：1998-12-15
申请号：US834562
申请日：1997-04-07
申请人： Mitsuharu Ohki , Takao Yamazaki , Masuyoshi Kurokawa , Akihiko Hashiguchi
发明人： Mitsuharu Ohki , Takao Yamazaki , Masuyoshi Kurokawa , Akihiko Hashiguchi
IPC分类号： G06F9/38 , G06F15/80 , G06T1/20 , H04N5/14 , H04N7/015 , H04N7/12
CPC分类号： G06F15/8015 , H04N5/14
摘要： To provide a parallel processor apparatus which can perform processing with a good efficiency on signals comprised of data of different lengths. A parallel processor configured by a serial connection of a first parallel processor and a second parallel processor having n number of individual processors and (m-n) number of individual processors. For signals comprised of data of a length, serving as the unit of processing, of m or less and n or more, these parallel processors are connected and used as a single parallel processor apparatus which performs processing equivalent to that by a conventional parallel processor apparatus. For signals comprised of data of a length of n or less, these parallel processors are independently used to perform pipeline processing and thereby perform two times the amount of processing of that performed by a conventional parallel processor apparatus.
摘要翻译：提供一种能够对由不同长度的数据组成的信号具有良好效率的处理的并行处理器装置。由第一并行处理器和具有n个单独处理器和（m-n个）个别处理器的数量的第一并行处理器和第二并行处理器的串行连接器配置的并行处理器。对于作为处理单位的长度为m以下且n以上的数据构成的信号，这些并行处理器被连接并用作执行与常规并行处理器装置相同的处理的单个并行处理器装置。对于由长度为n以下的数据构成的信号，这些并行处理器独立地用于执行流水线处理，从而执行由常规并行处理器装置执行的处理量的两倍。

2. 发明授权

US5666169A Parallel processor apparatus having means for processing signals of different lengths 失效
标题翻译：具有用于处理不同长度的信号的装置的并行处理器装置
公开(公告)号：US5666169A
公开(公告)日：1997-09-09
申请号：US519719
申请日：1995-08-28
申请人： Mitsuharu Ohki , Takao Yamazaki , Masuyoshi Kurokawa , Akihiko Hashiguchi
发明人： Mitsuharu Ohki , Takao Yamazaki , Masuyoshi Kurokawa , Akihiko Hashiguchi
IPC分类号： G06F9/38 , G06F15/80 , G06T1/20 , H04N5/14 , H04N7/015 , H04N5/46 , H04N7/12
CPC分类号： G06F15/8015 , H04N5/14
摘要： To provide a parallel processor apparatus which can perform processing with a good efficiency on signals comprised of data of different lengths. A parallel processor configured by a serial connection of a first parallel processor and a second parallel processor having n number of individual processors and (m-n) number of individual processors. For signals comprised of data of a length, serving as the unit of processing, of m or less and n or more, these parallel processors are connected and used as a single parallel processor apparatus which performs processing equivalent to that by a conventional parallel processor apparatus. For signals comprised of data of a length of n or less, these parallel processors are independently used to perform pipeline processing and thereby perform two times the amount of processing of that performed by a conventional parallel processor apparatus.
摘要翻译：提供一种能够对由不同长度的数据组成的信号具有良好效率的处理的并行处理器装置。由第一并行处理器和具有n个单独处理器和（m-n个）个别处理器的数量的第一并行处理器和第二并行处理器的串行连接器配置的并行处理器。对于作为处理单位的长度为m以下且n以上的数据构成的信号，这些并行处理器被连接并用作执行与常规并行处理器装置相同的处理的单个并行处理器装置。对于由长度为n以下的数据构成的信号，这些并行处理器独立地用于执行流水线处理，从而执行由常规并行处理器装置执行的处理量的两倍。

3. 发明授权

US06038350A Signal processing apparatus 失效
标题翻译：信号处理装置
公开(公告)号：US06038350A
公开(公告)日：2000-03-14
申请号：US228237
申请日：1999-01-11
申请人： Seiichiro Iwase , Masuyoshi Kurokawa , Takao Yamazaki , Mitsuharu Ohki
发明人： Seiichiro Iwase , Masuyoshi Kurokawa , Takao Yamazaki , Mitsuharu Ohki
IPC分类号： G06T1/20 , G06F15/80 , G06F17/10 , H04N5/14 , H04N5/46 , H04N5/926 , H04N11/00 , G06K9/36 , G06K9/54 , G06K9/60 , H04N1/40 , H04N7/12
CPC分类号： H04N5/14 , G06F17/10 , H04N5/926 , H04N11/002 , H04N5/46
摘要： A multiple parallel digital signal processor having a large number of bit processing processor elements arranged in one-dimensional array is treated as a processor block, and a plurality of the processor blocks are connected in sequence, while removing redundancy, to form a processor block column. A plurality of processor blocks are connected in sequence such that a processor block at a subsequent stage is supplied either with output of a processor block at a previous stage or with input data, and any of outputs of the processor block columns is delivered as a final output, thereby making it possible to realize a signal processing apparatus which has high performance, versatility, and simple configuration.
摘要翻译：具有以一维阵列排列的大量位处理处理器元件的多并行数字信号处理器被视为处理器块，并且多个处理器块依次连接，同时去除冗余，以形成处理器块列。多个处理器块被依次连接，使得在后一级的处理器块被提供在前一级的处理器块的输出或者与输入数据一起提供，并且处理器块列的任何一个输出作为最终的输出，从而可以实现具有高性能，多功能性和简单配置的信号处理装置。

4. 发明授权

US6052705A Video signal processor with triple port memory 失效
标题翻译：具有三端口存储器的视频信号处理器
公开(公告)号：US6052705A
公开(公告)日：2000-04-18
申请号：US701880
申请日：1996-08-23
申请人： Seiichiro Iwase , Masuyoshi Kurokawa , Takao Yamazaki , Mitsuharu Ohki
发明人： Seiichiro Iwase , Masuyoshi Kurokawa , Takao Yamazaki , Mitsuharu Ohki
IPC分类号： G06F12/04 , G06F7/575 , G06F15/80 , G09G5/00 , G11C11/401 , H03H17/02 , G06F7/32 , G06F7/38
CPC分类号： G06F7/575 , G06F2207/3896
摘要： A digital video signal processor using parallel processing includes an input serial-access memory having memory cells in which data is inputted into successive ones of the memory cells in response to a programmed-controlled pointer and a three or more port data memory unit for writing-in data read out from the serial-access memory. An arithmetic logic unit responds to stored-program control to read out data from the data memory, perform a program-prescribed arithmetic operation, and write the result of the arithmetic operation back to the data memory. An output serial-access memory is controlled so that the arithmetic result will be outputted under program control in a sequential manner. Operation of the interconnected components is effected by a stored-program control unit connected to the input serial-access memory, the data memory, the arithmetic logic unit, and the output serial-access memory.
摘要翻译：使用并行处理的数字视频信号处理器包括具有存储单元的输入串行存取存储器，其中响应于编程控制的指针将数据输入到存储单元的连续存储器单元中，以及三个或更多个端口数据存储单元，在从串行存取存储器读出的数据中。算术逻辑单元响应存储程序控制从数据存储器读出数据，执行程序规定的算术运算，并将算术运算结果写回数据存储器。控制输出串行存取存储器，使得算术结果以顺序方式在程序控制下输出。互连组件的操作由连接到输入串行存取存储器，数据存储器，算术逻辑单元和输出串行存取存储器的存储程序控制单元来实现。

5. 发明授权

US5926583A Signal processing apparatus 失效
标题翻译：信号处理装置
公开(公告)号：US5926583A
公开(公告)日：1999-07-20
申请号：US731161
申请日：1996-10-10
申请人： Seiichiro Iwase , Masuyoshi Kurokawa , Takao Yamazaki , Mitsuharu Ohki
发明人： Seiichiro Iwase , Masuyoshi Kurokawa , Takao Yamazaki , Mitsuharu Ohki
IPC分类号： G06T1/20 , G06F15/80 , G06F17/10 , H04N5/14 , H04N5/46 , H04N5/926 , H04N11/00 , G06K9/40 , G06K9/54 , H04N1/40 , H04N7/12
CPC分类号： H04N5/14 , G06F17/10 , H04N5/926 , H04N11/002 , H04N5/46
摘要： A multiple parallel digital signal processor having a large number of bit processing processor elements arranged in one-dimensional array is treated as a processor block, and a plurality of the processor blocks are connected in sequence, while removing redundancy, to form a processor block column. A plurality of processor blocks are connected in sequence such that a processor block at a subsequent stage is supplied either with output of a processor block at a previous stage or with input data, and an output of any of the processor blocks is delivered as a final output, thereby making it possible to realize a signal processing apparatus which has high performance, versatility, and simple configuration.
摘要翻译：具有以一维阵列排列的大量位处理处理器元件的多并行数字信号处理器被视为处理器块，并且多个处理器块依次连接，同时去除冗余，以形成处理器块列。多个处理器块被依次连接，使得在后一级的处理器块被提供在先前阶段的处理器块的输出或者与输入数据一起提供，并且任何处理器块的输出作为最终的输出，从而可以实现具有高性能，多功能性和简单配置的信号处理装置。

6. 发明授权

US5864706A Digital signal processing apparatus and information processing system 失效
标题翻译：数字信号处理装置及信息处理系统
公开(公告)号：US5864706A
公开(公告)日：1999-01-26
申请号：US693005
申请日：1996-08-06
申请人： Masuyoshi Kurokawa , Seiichiro Iwase , Takao Yamazaki , Kenichiro Nakamura
发明人： Masuyoshi Kurokawa , Seiichiro Iwase , Takao Yamazaki , Kenichiro Nakamura
IPC分类号： G06F15/80 , G06F15/78 , G06F12/00
CPC分类号： G06F15/7857
摘要： A digital signal processing apparatus and information processing system provide sufficient arithmetic operation performance to process high rate signals in real time and high programming performance to deal with various applications. A group of processor elements is constituted by individual processor elements each formed by disposing an arithmetic and logic unit on the bit lines of a multiport memory wherein their number is equal to or larger than the number of the data bits in a series of serial data, and the plurality of processor elements constituting the group of processor elements are uniformly controlled by controllers mounted on the same silicon chip. Consequently, the multiport memory functioning as a buffer for input data and the arithmetic and logic unit are closely joined together, so data can be communicated smoothly between them. Since the plurality of processor elements are controlled by a single controller so as to operate as a parallel computer, a digital signal processor with a high processing speed can be implemented.
摘要翻译：数字信号处理装置和信息处理系统提供足够的算术运算性能，以实时处理高速率信号和高编程性能来处理各种应用。一组处理器元件由各个处理器元件构成，每个处理器元件通过在多端口存储器的位线上设置算术和逻辑单元而形成，其中它们的数量等于或大于一系列串行数据中的数据位数，并且构成处理器元件组的多个处理器元件由安装在同一硅芯片上的控制器均匀地控制。因此，用作输入数据的缓冲器的多端口存储器和算术和逻辑单元紧密地连接在一起，因此可以在它们之间平滑地传送数据。由于多个处理器元件由单个控制器控制以便作为并行计算机操作，因此可以实现具有高处理速度的数字信号处理器。

7. 发明授权

US5689450A Parallel processor 失效
标题翻译：并行处理器
公开(公告)号：US5689450A
公开(公告)日：1997-11-18
申请号：US520175
申请日：1995-08-28
申请人： Masuyoshi Kurokawa , Takao Yamazaki
发明人： Masuyoshi Kurokawa , Takao Yamazaki
IPC分类号： G06F7/00 , G06F15/80 , G06T1/20 , G06F7/38
CPC分类号： G06T1/20 , G06F15/8015
摘要： A parallel processor for processing a plurality of pieces of data includes a number of unitary processing units provided in parallel equal to the number of pieces of data. Each of the unitary processing units includes a memory circuit connected to a processing element which exchanges data with two adjoining unitary processing units. Each of the processing elements includes a full adder, a logical operation circuit for performing a logical operation on two inputs connected to a first input of the full adder and a plurality of selector circuits. A first selector circuit selects first data from memory circuits of the unitary processing unit and an adjoining unitary processing unit. A second selector circuit selects second data from memory circuits of the unitary processing unit and an adjoining unitary processing unit. A third selector circuit selects the second data selected by the second selector circuit as a first input to the logical operation circuit. A fourth selector circuit selects the first data selected by the first selector circuit as a second input to the logical operation circuit. A fifth selector circuit selects the second data selected by the second selector circuit as a second input to the full adder. A sixth selector circuit selects the carrier output of the full adder as a third input to the full adder.
摘要翻译：用于处理多条数据的并行处理器包括并行提供的数个等于数据片数的单位处理单元。每个单一处理单元包括连接到与两个邻接的单一处理单元交换数据的处理元件的存储器电路。每个处理元件包括全加器，用于对连接到全加器的第一输入的两个输入和多个选择器电路执行逻辑运算的逻辑运算电路。第一选择器电路从单一处理单元的存储电路和相邻的一体处理单元中选择第一数据。第二选择器电路从单一处理单元的存储电路和相邻的单一处理单元中选择第二数据。第三选择器电路选择由第二选择器电路选择的第二数据作为逻辑运算电路的第一输入。第四选择器电路将由第一选择器电路选择的第一数据选择为逻辑运算电路的第二输入。第五选择器电路选择由第二选择器电路选择的第二数据作为全加器的第二输入。第六选择器电路选择全加器的载波输出作为全加器的第三输入。

8. 发明授权

US08374441B2 Image processing device, method, and program 有权
公开(公告)号：US08374441B2
公开(公告)日：2013-02-12
申请号：US12400936
申请日：2009-03-10
申请人： Koji Aoyama , Hideki Watanabe , Hiroaki Yamajo , Masuyoshi Kurokawa
发明人： Koji Aoyama , Hideki Watanabe , Hiroaki Yamajo , Masuyoshi Kurokawa
IPC分类号： G06K9/62
摘要： An image processing device includes: a step calculator configured to calculate, as a step, a difference in pixel values of pixels in a neighborhood with respect to each pixel in an image; a classifier configured to classify the pixels into classes for areas of the steps; a boundary ratio calculator configured to calculate, as a boundary ratio, a ratio of the number of pixels at a block boundary for each of the classes; and a block noise strength determinator configured to determine, as a block noise strength of the image, the step that is larger than a predetermined threshold and that is at a class having a largest value.

9. 发明授权

US07425990B2 Motion correction device and method 有权
标题翻译：运动校正装置及方法
公开(公告)号：US07425990B2
公开(公告)日：2008-09-16
申请号：US10521304
申请日：2004-05-12
申请人： Takaya Hoshino , Kazuhiko Nishibori , Toshio Sarugaku , Masuyoshi Kurokawa
发明人： Takaya Hoshino , Kazuhiko Nishibori , Toshio Sarugaku , Masuyoshi Kurokawa
IPC分类号： H04N5/14 , H04N7/01 , H04N9/64 , H04N11/20 , G06K9/32 , G06K9/40
CPC分类号： H04N7/014 , H04N5/145 , H04N5/253 , H04N7/012 , H04N7/0132
摘要： To realize a motion compensation device capable of more appropriately compensating the movement of a video signal subjected to double-speed conversion. A motion vector between an image of a current field in a double-speed-converted video signal and an image of a reference field that is one frame or two frames later is detected, the pixels of the current field are shifted based on the motion vector and the pixels of the reference field are shifted in an opposite direction based on the motion vector. Then simple averaging or weighted average according to the shift amount is performed on the pixels of the current field and the pixels of the reference field to compensate the current field, thereby being capable of compensating the movement between fields so as to be much smoother than conventional cases.
摘要翻译：实现能够更适当地补偿经受双速转换的视频信号的移动的运动补偿装置。检测双速转换视频信号中的当前场的图像与一帧或两帧后的参考场的图像之间的运动矢量，基于运动矢量移位当前场的像素并且参考场的像素基于运动矢量沿相反方向移位。然后，对当前场的像素和参考场的像素执行根据移位量的简单平均或加权平均以补偿电流场，从而能够补偿场之间的运动，以便比常规的更平滑案件

10. 发明授权

US07215377B2 Image signal processing apparatus and processing method 有权
标题翻译：图像信号处理装置及处理方法
公开(公告)号：US07215377B2
公开(公告)日：2007-05-08
申请号：US10498426
申请日：2002-12-13
申请人： Takaya Hoshino , Toshio Sarugaku , Ikuo Someya , Makoto Kondo , Kazuhiko Nishibori , Koji Aoyama , Yukihiko Mogi , Nobuo Ueki , Masuyoshi Kurokawa
发明人： Takaya Hoshino , Toshio Sarugaku , Ikuo Someya , Makoto Kondo , Kazuhiko Nishibori , Koji Aoyama , Yukihiko Mogi , Nobuo Ueki , Masuyoshi Kurokawa
IPC分类号： H04N7/01
CPC分类号： H04N7/0132 , H04N5/145 , H04N7/014 , Y10S348/91
摘要： The present invention provides an image signal processing apparatus and a method thereof in which each of the fields forming the unit-frame is specified, with respect to the inputted image signal, based on a difference value calculated in signal level between a detected pixel in a current field and a detected pixel at the same position in a field which comes one frame behind the current field, a motion vector for a field which comes two frames behind the current field is detected, with respect to the detected pixel in the current field, the detected pixel is shifted, with respect to the specified first field, in a direction opposite to the motion vector within the range of the detected motion vector, the detected pixel is shifted, with respect to the specified fourth field, in a direction along the motion vector, and the detected pixels is shifted, with respect to the specified second and third fields, so as to make the pixels gradually closer to the pixel position shifted with respect to the fourth field, in the consecutive order of the fields from the first field, in the direction along the motion vector or in the direction opposite to the motion vector.
摘要翻译：本发明提供了一种图像信号处理装置及其方法，其中，基于在信号电平中计算出的信号电平中的检测像素之间的差值，相对于输入的图像信号来指定形成单位帧的每个场当前场和位于当前场后面一帧的场中的相同位置处的检测像素，相对于当前场中的检测像素检测到在当前场后面两帧的场的运动矢量，检测到的像素相对于规定的第一场沿与检测到的运动矢量的范围内的运动矢量相反的方向移位，检测像素相对于规定的第四场沿着沿着运动矢量，并且检测像素相对于规定的第二和第三场移动，以使像素逐渐更接近于相对于相对移动的像素位置以与运动矢量相反的方向沿着运动矢量的方向以第一场的场的连续顺序，以第一场为单位。

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