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1. 发明授权

US07554849B2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US07554849B2
公开(公告)日：2009-06-30
申请号：US11940736
申请日：2007-11-15
申请人： Mitsuaki Honma , Katsuaki Isobe
发明人： Mitsuaki Honma , Katsuaki Isobe
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/20 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/48 , G11C2029/5004
摘要： A nonvolatile semiconductor memory for setting control voltages to be supplied to an internal circuit, to an external reference voltage inputted from outside, has a parameter control circuit. The parameter control circuit causes a parameter register to sequentially output the plurality of parameters to a voltage generating control circuit. The parameter control circuit counts, for a fixed period of time, the number of oscillations of each of the trimming flag signals sequentially outputted from the voltage generating control circuit in response to the parameters. The parameter control circuit stores counted values corresponding to the parameters. The parameter control circuit selects the parameter having a maximum counted value as a parameter corresponding to the control voltage closest to the external reference voltage.
摘要翻译：用于将向内部电路提供的控制电压设置为从外部输入的外部参考电压的非易失性半导体存储器具有参数控制电路。参数控制电路使参数寄存器顺序地将多个参数输出到电压产生控制电路。参数控制电路在固定的时间段内，根据参数从电压产生控制电路顺序输出的每个修整标志信号的振荡次数进行计数。参数控制电路存储对应于参数的计数值。参数控制电路选择具有最大计数值的参数作为与最接近外部参考电压的控制电压对应的参数。

2. 发明授权

US07808821B2 Nonvolatile semiconductor memory including memory cell for storing multilevel data having two or more values 有权
标题翻译：非易失性半导体存储器，包括用于存储具有两个或更多个值的多电平数据的存储单元
公开(公告)号：US07808821B2
公开(公告)日：2010-10-05
申请号：US12204207
申请日：2008-09-04
申请人： Mikio Ogawa , Katsuaki Isobe , Yoshikazu Takeyama , Mitsuaki Honma , Noboru Shibata
发明人： Mikio Ogawa , Katsuaki Isobe , Yoshikazu Takeyama , Mitsuaki Honma , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： A write controller performs verification for checking whether each memory cell is on a predetermined verification level. For a memory cell to be written to a voltage level higher than the predetermined verification level, the write controller stores, in first and second latch circuits, the number of times of write to be performed by a write voltage after the verification. Whenever write is performed by the write voltage, the write controller updates the number of times of write stored in the first and second latch circuits. After write is performed the number of times of write by the write voltage, the write controller performs write by an intermediate voltage lower than the write voltage.
摘要翻译：写入控制器执行用于检查每个存储单元是否处于预定验证级别的验证。对于要写入高于预定验证电平的电压电平的存储单元，写入控制器在第一和第二锁存电路中存储在验证之后由写入电压执行的写入次数。无论何时通过写入电压执行写入，写入控制器更新存储在第一和第二锁存电路中的写入次数。在通过写入电压执行写入次数之后，写入控制器通过低于写入电压的中间电压来执行写入。

3. 发明申请

US20080117687A1 NONVOLATILE SEMICONDUCTOR MEMORY 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20080117687A1
公开(公告)日：2008-05-22
申请号：US11940736
申请日：2007-11-15
申请人： Mitsuaki Honma , Katsuaki Isobe
发明人： Mitsuaki Honma , Katsuaki Isobe
IPC分类号： G11C16/08 , G11C8/00
CPC分类号： G11C16/0483 , G11C16/20 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/48 , G11C2029/5004
摘要： A nonvolatile semiconductor memory for setting control voltages to be supplied to an internal circuit, to an external reference voltage inputted from outside, has a parameter control circuit. The parameter control circuit causes a parameter register to sequentially output the plurality of parameters to a voltage generating control circuit. The parameter control circuit counts, for a fixed period of time, the number of oscillations of each of the trimming flag signals sequentially outputted from the voltage generating control circuit in response to the parameters. The parameter control circuit stores counted values corresponding to the parameters. The parameter control circuit selects the parameter having a maximum counted value as a parameter corresponding to the control voltage closest to the external reference voltage.
摘要翻译：用于将向内部电路提供的控制电压设置为从外部输入的外部参考电压的非易失性半导体存储器具有参数控制电路。参数控制电路使参数寄存器顺序地将多个参数输出到电压产生控制电路。参数控制电路在固定的时间段内，根据参数从电压产生控制电路顺序输出的每个修整标志信号的振荡次数进行计数。参数控制电路存储对应于参数的计数值。参数控制电路选择具有最大计数值的参数作为与最接近外部参考电压的控制电压对应的参数。

4. 发明申请

US20090067255A1 NONVOLATILE SEMICONDUCTOR MEMORY INCLUDING MEMORY CELL FOR STORING MULTILEVEL DATA HAVING TWO OR MORE VALUES 有权
标题翻译：非易失性半导体存储器，包括用于存储具有两个或多个值的多个数据的存储器单元
公开(公告)号：US20090067255A1
公开(公告)日：2009-03-12
申请号：US12204207
申请日：2008-09-04
申请人： Mikio OGAWA , Katsuaki Isobe , Yoshikazu Takeyama , Mitsuaki Honma , Noboru Shibata
发明人： Mikio OGAWA , Katsuaki Isobe , Yoshikazu Takeyama , Mitsuaki Honma , Noboru Shibata
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： A write controller performs verification for checking whether each memory cell is on a predetermined verification level. For a memory cell to be written to a voltage level higher than the predetermined verification level, the write controller stores, in first and second latch circuits, the number of times of write to be performed by a write voltage after the verification. Whenever write is performed by the write voltage, the write controller updates the number of times of write stored in the first and second latch circuits. After write is performed the number of times of write by the write voltage, the write controller performs write by an intermediate voltage lower than the write voltage.
摘要翻译：写入控制器执行用于检查每个存储单元是否处于预定验证级别的验证。对于要写入高于预定验证电平的电压电平的存储单元，写入控制器在第一和第二锁存电路中存储在验证之后由写入电压执行的写入次数。无论何时通过写入电压执行写入，写入控制器更新存储在第一和第二锁存电路中的写入次数。在通过写入电压执行写入次数之后，写入控制器通过低于写入电压的中间电压来执行写入。

5. 发明授权

US08315110B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US08315110B2
公开(公告)日：2012-11-20
申请号：US13315967
申请日：2011-12-09
申请人： Hideo Mukai , Hiroshi Maejima , Katsuaki Isobe
发明人： Hideo Mukai , Hiroshi Maejima , Katsuaki Isobe
IPC分类号： G11C7/10
摘要： A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a first and second drive circuit selecting the first and second lines connected to the memory cells of each MAT that are accessed, and driving the selected first and second lines to write or read data. The memory cells form a page by being connected to each first line selected from the MATs. The device also includes a data latch latching the write or the read data in units of pages, where the first and second drive circuit drive the first and second lines multiple times to write or read data for one page in and out of the cell array.

6. 发明申请

US20110235417A1 NAND FLASH MEMORY 审中-公开
标题翻译： NAND闪存
公开(公告)号：US20110235417A1
公开(公告)日：2011-09-29
申请号：US13154522
申请日：2011-06-07
申请人： Katsuaki Isobe
发明人： Katsuaki Isobe
IPC分类号： G11C16/02
CPC分类号： G11C8/08 , G11C8/10 , G11C16/0483
摘要： A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and composed of a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at the gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at the gate thereof; a row decoder that is connected to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array, and applies a signal voltage to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array for selecting a block; and a sense amplifier that is controlled by a column decoder and makes a selection from said bit lines of said memory cell array, wherein, in a block that is not selected by said row decoder, said bit line selected by said sense amplifier is charged in a state where the drain-side select gate line, the source-side select gate line and the p-type semiconductor substrate are set at a ground potential, and the source lines, the n-type wells, the p-type wells and a bit line that is not selected by said sense amplifier are in a floating state.
摘要翻译：在选择的位线和非选择的位线彼此相邻时读取的NAND快闪存储器具有存储单元阵列，其具有多个块，每个块由多个存储单元单元组成，每个块由多个存储单元单元组成所述存储单元具有多个电可重写存储单元，它们彼此连接并且由形成在p型半导体衬底中的n型阱围绕的p型阱组成，每个漏极侧选择栅晶体管其将存储单元单元连接到位线并连接到其栅极处的漏极侧选择栅极线，以及源极选择栅极晶体管，每个源极选择栅极晶体管将存储单元单元连接到源极线并连接到源极选择栅极线; 连接到所述存储单元阵列的字线，漏极侧选择栅极线和源极侧栅极线的行解码器，并将信号电压施加到字线，漏极侧选择栅极线和源极侧选择栅极线，所述存储单元阵列的侧栅极线用于选择块; 以及由列解码器控制并从所述存储单元阵列的所述位线进行选择的读出放大器，其中，在未被所述行解码器选择的块中，由所述读出放大器选择的所述位线被充电漏极侧选择栅极线，源极侧选择栅极线和p型半导体衬底设置为接地电位的状态，源极线，n型阱，p型阱和a 未被所述读出放大器选择的位线处于浮置状态。

7. 发明申请

US20110134695A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20110134695A1
公开(公告)日：2011-06-09
申请号：US12957865
申请日：2010-12-01
申请人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
发明人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
IPC分类号： G11C16/04
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： Provided is a semiconductor memory device including: multiple bit lines arranged in parallel to one another; multiple sense-amplifier bit lines arranged away from end portions of the bit lines; a fourth sense-amplifier bit line formed with a wire of a first layer arranged below the bit lines; selection transistors with a pair of gate electrodes arranged in a direction normal to the first to sixth bit lines; a first wire arranged below the bit lines and the sense-amplifier bit lines, and having an end portion extending to below the third bit line and connected to the bit line; a third wire formed with a layer of the gate electrode used as a wire, the third wire including a first end portion positioned below the fourth sense-amplifier bit line and connected to the fourth sense-amplifier bit line, and a second end portion positioned below the second sense-amplifier bit line; and a fourth wire formed with a wire of the first layer and arranged between the third wire and the second sense-amplifier bit line to connect the third wire to the second sense-amplifier bit line.
摘要翻译：提供一种半导体存储器件，包括：彼此平行布置的多个位线; 多个读出放大器位线布置成远离位线的端部; 第四感测放大器位线，其布置在位线下方的第一层的导线; 选择晶体管，其具有沿与第一至第六位线垂直的方向排列的一对栅电极; 布置在位线下方的第一线和读出放大器位线，并且具有延伸到第三位线下方并连接到位线的端部; 第三线，其形成有用作线的栅极电极层，所述第三线包括位于所述第四感测放大器位线下方并连接到所述第四感测放大器位线的第一端部，以及位于低于第二感测放大器位线; 以及第四导线，其由第一层的导线形成，并且布置在第三导线和第二读出放大器位线之间，以将第三导线连接到第二感测放大器位线。

8. 发明授权

US07916541B2 NAND flash memory 有权
标题翻译： NAND闪存
公开(公告)号：US07916541B2
公开(公告)日：2011-03-29
申请号：US12642503
申请日：2009-12-18
申请人： Hiroshi Maejima , Katsuaki Isobe
发明人： Hiroshi Maejima , Katsuaki Isobe
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/0483
摘要： A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.
摘要翻译：读取操作中的NAND闪速存储器设置为接地电位，将位线充电至第一电压，将源极线，n型阱和p型阱充电位于接地电位和第一电压之间的第二电压，并且在未被所述行解码器选择的块中，所述漏极侧选择栅极线和所述源极侧选择栅极线被充电到第三电压，其中高于所述接地电位，并且等于或低于所述第二电压。

9. 发明授权

US07817468B2 Semiconductor storage device provided with memory cell having charge accumulation layer and control gate 有权
标题翻译：设置有具有电荷累积层和控制栅极的存储单元的半导体存储装置
公开(公告)号：US07817468B2
公开(公告)日：2010-10-19
申请号：US12365590
申请日：2009-02-04
申请人： Katsuaki Isobe , Noboru Shibata
发明人： Katsuaki Isobe , Noboru Shibata
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5635 , G11C16/12 , G11C16/16 , G11C16/3418
摘要： A semiconductor memory device includes memory cell transistors, a first selection transistor, and word lines. Each of the memory cell transistors has a stacked gate including a charge accumulation layer and a control gate, and is configured to retain at least two levels of “0” data and “1” data according to a threshold voltage. The threshold voltage corresponding to the “0” data being the lowest threshold voltage in the levels retained by each of the memory cell transistors. The first selection transistor has a current path connected in series to one of the memory cell transistors. Each of the word lines is connected to the control gate of one of the memory cell transistors. upper limit values of threshold voltages of the memory cell transistors retaining the “0” data being different from one another in each word line.
摘要翻译：半导体存储器件包括存储单元晶体管，第一选择晶体管和字线。每个存储单元晶体管具有包括电荷累积层和控制栅极的堆叠栅极，并且被配置为根据阈值电压保持至少两个级别的“0”数据和“1”数据。对应于“0”数据的阈值电压是由每个存储单元晶体管保持的电平中的最低阈值电压。第一选择晶体管具有与存储单元晶体管之一串联连接的电流通路。每个字线连接到存储单元晶体管之一的控制栅极。保持“0”数据的存储单元晶体管的阈值电压的上限值在每个字线中彼此不同。

10. 发明授权

US07697333B2 NAND flash memory 失效
标题翻译： NAND闪存
公开(公告)号：US07697333B2
公开(公告)日：2010-04-13
申请号：US11836378
申请日：2007-08-09
申请人： Katsuaki Isobe
发明人： Katsuaki Isobe
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C8/10 , G11C16/0483
摘要： A NAND flash memory including a memory cell array having a plurality of blocks, each of the blocks is composed of a plurality of memory cell units, drain-side select gate transistors, and source-side select gate transistors. The NAND flash memory further includes a row decoder that is connected to word lines, the drain-side select gate lines, and the source-side gate line of the memory cell array, and that applies a signal voltage to word lines, the drain-side select gate lines and the source-side gate line of the memory cell array for selecting blocks. The NAND flash memory further includes a sense amplifier that is controlled by a column decoder and that makes a selection from the bit lines of the memory cell array.
摘要翻译：包括具有多个块的存储单元阵列的NAND闪速存储器，每个块由多个存储单元单元，漏极侧选择栅极晶体管和源极侧选择栅极晶体管组成。 NAND闪存还包括连接到字线，漏极侧选择栅极线和存储单元阵列的源极侧栅极线的行解码器，并且对字线施加信号电压，选择栅极线和用于选择块的存储单元阵列的源极侧栅极线。 NAND闪存还包括由列解码器控制并且从存储单元阵列的位线进行选择的读出放大器。

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