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1. 发明授权

US08208320B2 Semiconductor device having reset command 有权
标题翻译：具有复位命令的半导体器件
公开(公告)号：US08208320B2
公开(公告)日：2012-06-26
申请号：US12727860
申请日：2010-03-19
申请人： Kazushige Kanda
发明人： Kazushige Kanda
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00
CPC分类号： G11C7/20 , G11C5/14 , G11C5/143 , G11C13/0061 , G11C16/32
摘要： A semiconductor device includes a reset sequence circuit, a latch circuit, and a reset control circuit. The reset sequence circuit is activated by receiving an externally input signal when a reset operation is started and outputs a first trigger signal. The latch circuit is capable of holding selection information on circuits capable of being reset. The selection information is externally input. The reset control circuit outputs a reset signal on the basis of the selection information held in the latch circuit in response to a power-on reset signal and the first trigger signal output from the reset sequence circuit.
摘要翻译：半导体器件包括复位顺序电路，锁存电路和复位控制电路。当复位操作开始时，通过接收外部输入信号来激活复位顺序电路并输出第一触发信号。锁存电路能够保持能够复位的电路的选择信息。选择信息是外部输入的。复位控制电路响应于上电复位信号和从复位顺序电路输出的第一触发信号，基于保持在锁存电路中的选择信息输出复位信号。

2. 发明授权

US08195993B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08195993B2
公开(公告)日：2012-06-05
申请号：US13178982
申请日：2011-07-08
申请人： Yuki Okukawa , Kazushige Kanda
发明人： Yuki Okukawa , Kazushige Kanda
IPC分类号： G11C29/00
CPC分类号： G01R31/3183 , G01R31/31919 , G11C16/04 , G11C29/028 , G11C29/48 , G11C29/50 , G11C29/56
摘要： A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.
摘要翻译：与本发明的实施例有关的半导体集成电路装置包括地址寄存器，其包括与控制电路连接的内部选择电路，指示控制电路以产生预定的内部控制信号的信号生成指令电路，锁存电路，其中多个对应于测试参数数据的位数排列，锁存电路锁存从数据程序/读取电路提供的测试结果数据，并将测试结果数据输出到选择电路和外部，所述控制电路产生内部控制信号，所述内部控制信号在所述测试参数数据的固定值数据被改变的定时激活所述选择电路，并且所述选择电路控制测试，使得所述测试参数数据的固定值数据被改变。

3. 发明申请

US20110264969A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20110264969A1
公开(公告)日：2011-10-27
申请号：US13178982
申请日：2011-07-08
申请人： Yuki OKUKAWA , Kazushige Kanda
发明人： Yuki OKUKAWA , Kazushige Kanda
IPC分类号： G11C29/00
CPC分类号： G01R31/3183 , G01R31/31919 , G11C16/04 , G11C29/028 , G11C29/48 , G11C29/50 , G11C29/56
摘要： A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.
摘要翻译：与本发明的实施例有关的半导体集成电路装置包括地址寄存器，其包括与控制电路连接的内部选择电路，指示控制电路以产生预定的内部控制信号的信号生成指令电路，锁存电路，其中多个对应于测试参数数据的位数排列，锁存电路锁存从数据程序/读取电路提供的测试结果数据，并将测试结果数据输出到选择电路和外部，所述控制电路产生内部控制信号，所述内部控制信号在所述测试参数数据的固定值数据被改变的定时激活所述选择电路，并且所述选择电路控制测试，使得所述测试参数数据的固定值数据被改变。

4. 发明授权

US08006145B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08006145B2
公开(公告)日：2011-08-23
申请号：US12415448
申请日：2009-03-31
申请人： Yuki Okukawa , Kazushige Kanda
发明人： Yuki Okukawa , Kazushige Kanda
IPC分类号： G11C29/00
CPC分类号： G01R31/3183 , G01R31/31919 , G11C16/04 , G11C29/028 , G11C29/48 , G11C29/50 , G11C29/56
摘要： A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.
摘要翻译：与本发明的实施例有关的半导体集成电路装置包括地址寄存器，其包括与控制电路连接的内部选择电路，指示控制电路以产生预定的内部控制信号的信号生成指令电路，锁存电路，其中多个对应于测试参数数据的位数排列，锁存电路锁存从数据程序/读取电路提供的测试结果数据，并将测试结果数据输出到选择电路和外部，所述控制电路产生内部控制信号，所述内部控制信号在所述测试参数数据的固定值数据被改变的定时激活所述选择电路，并且所述选择电路控制测试，使得所述测试参数数据的固定值数据被改变。

5. 发明授权

US08000155B2 Non-volatile memory device and method for writing data thereto 有权
公开(公告)号：US08000155B2
公开(公告)日：2011-08-16
申请号：US13005582
申请日：2011-01-13
申请人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C7/22 , G11C7/06 , G11C11/00 , G11C17/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.

6. 发明授权

US07889558B2 Nonvolatile semiconductor memory device in which an amount of data to be stored in a memory cell is allocated to every other word line units of one word line 有权
标题翻译：非易失性半导体存储器件，其中要存储在存储单元中的数据量被分配给一个字线的每隔一个字线单元
公开(公告)号：US07889558B2
公开(公告)日：2011-02-15
申请号：US12028480
申请日：2008-02-08
申请人： Kazushige Kanda
发明人： Kazushige Kanda
IPC分类号： G11C16/04
CPC分类号： G11C11/5621 , G11C16/0483 , G11C16/3418 , G11C2211/5641
摘要： A nonvolatile semiconductor memory device having a plurality of word lines and a plurality of bit lines and a plurality of sense amplifiers, each amplifier being connected to one of the plurality of bit lines respectively and a memory cell array including a memory cell region including a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, each of the memory cells having two or more storage states, said plurality of memory cells being connected to a corresponding word line of the plurality of word lines respectively, the plurality of memory strings being connected to a corresponding bit line of the plurality of bit lines respectively, and at the time of programming all of the plurality of bit lines are selected, the number of the storage states being different in two of the memory cells which are adjacent on the same bit line.
摘要翻译：一种非易失性半导体存储器件，具有多个字线和多个位线和多个读出放大器，每个放大器分别连接到所述多个位线中的一个位线;以及存储单元阵列，其包括存储单元区域，所述存储单元区域包括多个具有串联连接的多个电可重新编程存储单元的存储器串，每个存储单元具有两个或多个存储状态，所述多个存储单元分别连接到所述多个字线中的相应字线，存储器串分别连接到多个位线的对应位线，并且在编程时，选择所有多个位线，存储状态的数量在相邻的两个存储器单元中不同在同一位线上。

7. 发明申请

US20100246280A1 SEMICONDUCTOR DEVICE HAVING RESET COMMAND 有权
标题翻译：具有复位指令的半导体器件
公开(公告)号：US20100246280A1
公开(公告)日：2010-09-30
申请号：US12727860
申请日：2010-03-19
申请人： Kazushige KANDA
发明人： Kazushige KANDA
IPC分类号： G11C7/10 , H03L7/00 , G11C11/00 , G11C16/04
CPC分类号： G11C7/20 , G11C5/14 , G11C5/143 , G11C13/0061 , G11C16/32
摘要： A semiconductor device includes a reset sequence circuit, a latch circuit, and a reset control circuit. The reset sequence circuit is activated by receiving an externally input signal when a reset operation is started and outputs a first trigger signal. The latch circuit is capable of holding selection information on circuits capable of being reset. The selection information is externally input. The reset control circuit outputs a reset signal on the basis of the selection information held in the latch circuit in response to a power-on reset signal and the first trigger signal output from the reset sequence circuit.
摘要翻译：半导体器件包括复位顺序电路，锁存电路和复位控制电路。当复位操作开始时，通过接收外部输入信号来激活复位顺序电路并输出第一触发信号。锁存电路能够保持能够复位的电路的选择信息。选择信息是外部输入的。复位控制电路响应于上电复位信号和从复位顺序电路输出的第一触发信号，基于保持在锁存电路中的选择信息输出复位信号。

8. 发明授权

US07505355B2 Semiconductor memory device with MOS transistors each having floating gate and control gate 有权
标题翻译：具有MOS晶体管的半导体存储器件分别具有浮动栅极和控制栅极
公开(公告)号：US07505355B2
公开(公告)日：2009-03-17
申请号：US11733796
申请日：2007-04-11
申请人： Kazushige Kanda , Akira Umezawa , Kazuhiko Kakizoe , Yoshiaki Hashiba , Yoshiharu Hirata
发明人： Kazushige Kanda , Akira Umezawa , Kazuhiko Kakizoe , Yoshiaki Hashiba , Yoshiharu Hirata
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/08 , G11C11/005 , G11C16/0425 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , H01L27/115
摘要： A semiconductor memory device includes a memory cell array, word lines, and a row decoder. The memory cell array includes memory cells arranged in a matrix. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor. The word line connects the control gates of the first MOS transistors. The row decoder includes a first address decode circuit, a second address decode circuit, and a transfer gate. The first address decode circuit decodes m bits in a n-bit row address signal (m and n are a natural number satisfying the expression m
摘要翻译：半导体存储器件包括存储单元阵列，字线和行解码器。存储单元阵列包括排列成矩阵的存储单元。存储单元包括具有电荷累积层的第一MOS晶体管和控制栅极和第二MOS晶体管。字线连接第一MOS晶体管的控制栅极。行解码器包括第一地址解码电路，第二地址解码电路和传输门。第一地址解码电路解码n位行地址信号中的m位（m和n是满足表达式m

9. 发明授权

US07372761B2 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used 有权
标题翻译：半导体器件，非易失性半导体存储器，包括多个半导体器件或非易失性半导体存储器的系统，包括半导体器件或非易失性半导体存储器的电卡，以及可以使用该电卡的电子器件
公开(公告)号：US07372761B2
公开(公告)日：2008-05-13
申请号：US11521694
申请日：2006-09-15
申请人： Kazushige Kanda , Koichi Kawai , Hiroshi Nakamura , Kenichi Imamiya
发明人： Kazushige Kanda , Koichi Kawai , Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： G11C7/00
CPC分类号： G11C7/1063 , G11C7/1051 , G11C7/20 , G11C16/20 , G11C16/30
摘要： The object is to avoid an erroneous operation during a term in which an initialization is performed when a command is input.After a power source is turned on, a low level of a power-on-reset signal PWONRSTn is output until it reaches a power-on detect level. It is inverted by an inverter IN11, and input to a NOR circuit NR 11 likewise commands 1 and 2, so that a status is set to a busy status. The busy status is kept during a term in which a initialization operation is performed until the power supply voltage reaches the power-on detect level. Further, the status is read out to the exterior by a status read out mode signal to notify a user. As a result, it prevents from being input a command by an erroneous operation of a user during the initialization operation term.
摘要翻译：目的是避免在输入命令时执行初始化的术语期间的错误操作。电源接通后，输出低电平上电复位信号PWONRSTn，直到达到上电检测电平。它由反相器IN11反相，并且输入到NOR电路NR11同样命令1和2，使得状态被设置为忙状态。在执行初始化操作的期间内保持忙碌状态，直到电源电压达到上电检测电平。此外，通过状态读出模式信号将状态读出到外部，以通知用户。结果，它防止了在初始化操作期间通过用户的错误操作来输入命令。

10. 发明申请

US20080074941A1 Semiconductor Device, Nonvolatile Semiconductor Memory, System Including A Plurality Of Semiconductor Devices Or Nonvolatile Semiconductor Memories, Electric Card Including Semiconductor Device Or Nonvolatile Semiconductor Memory, And Electric Device With Which This Electric Card Can Be Used 有权
标题翻译：半导体器件，非易失性半导体存储器，包括多个半导体器件或非易失性半导体存储器的系统，包括半导体器件或非易失性半导体存储器的电卡以及可以使用该电卡的电气设备
公开(公告)号：US20080074941A1
公开(公告)日：2008-03-27
申请号：US11938756
申请日：2007-11-12
申请人： Kazushige KANDA , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi , Tamio Ikehashi
发明人： Kazushige KANDA , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi , Tamio Ikehashi
IPC分类号： G11C5/14
CPC分类号： G11C5/143 , G11C17/18
摘要： A semiconductor device of this invention includes a first circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, a second circuit for controlling the output from the first circuit by activation or deactivation, and an activation control circuit for activating or deactivating the second circuit in accordance with external input.
摘要翻译：本发明的半导体器件包括用于根据电源电压的电平初始化预定电路的第一电路，用于通过激活或去激活来控制来自第一电路的输出的第二电路，以及用于激活或去激活的激活控制电路，根据外部输入禁用第二电路。

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