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1. 发明授权

US08755246B2 Semiconductor memory device and method of setting operation environment therein 有权
标题翻译：半导体存储器件及其中的操作环境的设定方法
公开(公告)号：US08755246B2
公开(公告)日：2014-06-17
申请号：US13423608
申请日：2012-03-19
申请人： Kazushige Kanda , Toshihiro Suzuki
发明人： Kazushige Kanda , Toshihiro Suzuki
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C7/1045
摘要： A semiconductor memory device is provided, including a memory cell array having a plurality of memory cells; an internal circuit having a function required in a storage operation of the memory cell array; a parameter storage unit configured to store a certain parameter and to have a storage place specified by a parameter address, the certain parameter designating an operation of the internal circuit; a command register configured to store a command instructing an operation of the internal circuit; and a converting circuit configured to adjust at least one of the parameter address and the command that differ between products or between standards to the internal circuit.
摘要翻译：提供一种半导体存储器件，包括具有多个存储单元的存储单元阵列; 具有存储单元阵列的存储操作所需功能的内部电路; 参数存储单元，被配置为存储特定参数并且具有由参数地址指定的存储位置，所述特定参数指定所述内部电路的操作; 命令寄存器，被配置为存储指示所述内部电路的操作的命令; 以及转换电路，被配置为将产品之间或标准之间不同的参数地址和命令中的至少一个调整到内部电路。

2. 发明申请

US20120069530A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120069530A1
公开(公告)日：2012-03-22
申请号：US13234426
申请日：2011-09-16
申请人： Satoshi Inoue , Kazushige Kanda , Yuui Shimizu
发明人： Satoshi Inoue , Kazushige Kanda , Yuui Shimizu
IPC分类号： H05K7/00 , H01L21/66
CPC分类号： H01L24/97 , G11C5/025 , H01L21/76898 , H01L22/22 , H01L23/3107 , H01L23/481 , H01L23/4951 , H01L23/49575 , H01L24/16 , H01L24/48 , H01L25/0657 , H01L2224/13009 , H01L2224/4826 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01058 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/1203 , H01L2924/13091 , H01L2924/1431 , H01L2924/1434 , H01L2924/1438 , H01L2924/181 , H01L2224/81 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： According to one embodiment, a semiconductor device includes a stacked chip includes semiconductor chips which are stacked, the semiconductor chips comprises semiconductor substrates and through electrodes formed in the semiconductor substrates, respectively, the through electrodes being electrically connected, and deactivating circuits provided in the semiconductor chips, respectively, and configured to deactivate a failed semiconductor chip.
摘要翻译：根据一个实施例，半导体器件包括堆叠的芯片，其包括堆叠的半导体芯片，半导体芯片分别包括半导体衬底和通过形成在半导体衬底中的电极，通电电极被电连接，以及设置在半导体中的钝化电路芯片，并且被配置为去激活故障半导体芯片。

3. 发明申请

US20120002457A1 SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20120002457A1
公开(公告)日：2012-01-05
申请号：US13230156
申请日：2011-09-12
申请人： Kazushige KANDA
发明人： Kazushige KANDA
IPC分类号： G11C8/06 , G11C11/00 , G11C7/00 , G11C8/00
CPC分类号： G11C13/00 , G11C7/1021 , G11C7/22 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/51 , G11C2213/71 , G11C2213/72
摘要： According to one embodiment, a semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, and a data input/output circuit includes a first address buffer and a second address buffer configured to store a first address and a second address of the plurality of memory cells, and a controller configured to perform control to time-divisionally output the first address and the second address to a first address bus and a second address bus in data input/output.
摘要翻译：根据一个实施例，半导体存储器件包括多个存储单元阵列，每个存储单元阵列包括多个存储单元，多个存储单元阵列堆叠在半导体衬底上以形成三维结构，以及数据输入/输出电路包括：第一地址缓冲器和第二地址缓冲器，被配置为存储多个存储器单元的第一地址和第二地址;以及控制器，被配置为执行控制以将第一地址和第二地址时分输出到第一地址地址总线和数据输入/输出中的第二个地址总线。

4. 发明授权

US07911823B2 Method of programming a non-volatile memory device 有权
标题翻译：编程非易失性存储器件的方法
公开(公告)号：US07911823B2
公开(公告)日：2011-03-22
申请号：US12123827
申请日：2008-05-20
申请人： Takuya Futatsuyama , Koji Hosono , Toshiaki Edahiro , Naoya Tokiwa , Kazushige Kanda , Shigeo Ohshima
发明人： Takuya Futatsuyama , Koji Hosono , Toshiaki Edahiro , Naoya Tokiwa , Kazushige Kanda , Shigeo Ohshima
IPC分类号： G11C11/00 , G11C7/00 , G11C7/02 , G11C7/12 , G11C8/08
CPC分类号： G11C11/36
摘要： A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.
摘要翻译：一种使用由可变电阻元件形成并且设置在字线和位线之间的存储单元来编程非易失性存储器件的方法包括：预先对所选择的字线和所选择的位线以及未选择的字线和非选择位线达到一定电压; 并且进一步对所选字线和未选择的位线进行充电，直到分别高于特定电压和编程块电压的编程电压，并同时对所选择的位线进行放电。

5. 发明授权

US07817457B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07817457B2
公开(公告)日：2010-10-19
申请号：US12132972
申请日：2008-06-04
申请人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohshima
发明人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohshima
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0097 , G11C2013/0092 , G11C2213/32 , G11C2213/72
摘要： According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.
摘要翻译：根据一个实施例，非易失性存储器件包括：存储单元阵列，其包括各自具有用于非易失性地存储由电可重写电阻值识别的数据的可变电阻元件的存储单元; 存储要写入存储单元阵列的给定组的存储单元的用于写入和擦除操作的写入和擦除数据的第一数据锁存器; 以及第二数据锁存器，存储用于执行给定组的补偿操作以补偿伴随着写入或擦除操作的写入和擦除干扰的参考数据。

6. 发明授权

US07633826B2 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used 有权
标题翻译：半导体器件，非易失性半导体存储器，包括多个半导体器件或非易失性半导体存储器的系统，包括半导体器件或非易失性半导体存储器的电卡，以及可以使用该电卡的电子器件
公开(公告)号：US07633826B2
公开(公告)日：2009-12-15
申请号：US11938756
申请日：2007-11-12
申请人： Kazushige Kanda , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi , Tamio Ikehashi
发明人： Kazushige Kanda , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi , Tamio Ikehashi
IPC分类号： G11C7/00
CPC分类号： G11C5/143 , G11C17/18
摘要： A semiconductor device of this invention includes a first circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, a second circuit for controlling the output from the first circuit by activation or deactivation, and an activation control circuit for activating or deactivating the second circuit in accordance with external input.
摘要翻译：本发明的半导体器件包括用于根据电源电压的电平初始化预定电路的第一电路，用于通过激活或去激活来控制来自第一电路的输出的第二电路，以及用于激活或去激活的激活控制电路，根据外部输入禁用第二电路。

7. 发明申请

US20090052227A1 NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO 有权
标题翻译：非易失性存储器件及其数据写入方法
公开(公告)号：US20090052227A1
公开(公告)日：2009-02-26
申请号：US12118064
申请日：2008-05-09
申请人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C11/00 , G11C7/00 , G11C7/06
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.
摘要翻译：本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件系列。根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

8. 发明申请

US20080205148A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20080205148A1
公开(公告)日：2008-08-28
申请号：US12028480
申请日：2008-02-08
申请人： Kazushige KANDA
发明人： Kazushige KANDA
IPC分类号： G11C16/06 , G11C17/16
CPC分类号： G11C11/5621 , G11C16/0483 , G11C16/3418 , G11C2211/5641
摘要： A nonvolatile semiconductor memory device having a plurality of word lines and a plurality of bit lines and a plurality of sense amplifiers, each amplifier being connected to one of the plurality of bit lines respectively and a memory cell array including a memory cell region including a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, each of the memory cells having two or more storage states, said plurality of memory cells being connected to a corresponding word line of the plurality of word lines respectively, the plurality of memory strings being connected to a corresponding bit line of the plurality of bit lines respectively, and at the time of programming all of the plurality of bit lines are selected, the number of the storage states being different in two of the memory cells which are adjacent on the same bit line.
摘要翻译：一种非易失性半导体存储器件，具有多个字线和多个位线和多个读出放大器，每个放大器分别连接到所述多个位线中的一个位线;以及存储单元阵列，其包括存储单元区域，所述存储单元区域包括多个具有串联连接的多个电可重新编程存储单元的存储器串，每个存储单元具有两个或多个存储状态，所述多个存储单元分别连接到所述多个字线中的相应字线，存储器串分别连接到多个位线的对应位线，并且在编程时，选择所有多个位线，存储状态的数量在相邻的两个存储器单元中不同在同一位线上。

9. 发明申请

US20080055985A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20080055985A1
公开(公告)日：2008-03-06
申请号：US11849752
申请日：2007-09-04
申请人： Kazushige KANDA
发明人： Kazushige KANDA
IPC分类号： G11C16/04
CPC分类号： G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C2211/5641
摘要： A non-volatile semiconductor memory device includes plurality of word lines and a plurality of bit lines comprising even numbered bit lines and odd numbered bit lines and a memory cell array including a plurality of memory cells having two or more storage states, one of the plurality of memory cells being connected to a corresponding word line of the plurality of word lines, the number of storage states between adjacent memory cells is different in a word line direction and a bit line direction.
摘要翻译：非易失性半导体存储器件包括多个字线和包括偶数位线和奇数位线的多个位线，以及包括具有两个或多个存储状态的多个存储单元的存储单元阵列，多个存储器单元中的一个的存储单元连接到多个字线的对应字线，相邻存储单元之间的存储状态数在字线方向和位线方向上不同。

10. 发明授权

US07209388B2 Semiconductor memory device with MOS transistors each having floating gate and control gate 失效
标题翻译：具有MOS晶体管的半导体存储器件分别具有浮动栅极和控制栅极
公开(公告)号：US07209388B2
公开(公告)日：2007-04-24
申请号：US11169633
申请日：2005-06-30
申请人： Kazushige Kanda
发明人： Kazushige Kanda
IPC分类号： G11C5/14
CPC分类号： G11C29/846 , G11C8/18 , G11C16/0433 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C29/808
摘要： A semiconductor memory device includes a row address transition detector. The semiconductor memory device remedies a fault by replacing a column in a memory cell array with a redundancy bit line. The row address transition detector detects a change in a row address signal for selecting the row direction of the memory cell array. Only when a change in the row address signal is detected by the row address transition detector, the redundancy bit line is sensed.
摘要翻译：半导体存储器件包括行地址转换检测器。半导体存储器件通过用冗余位线替换存储单元阵列中的列来补救故障。行地址转换检测器检测用于选择存储单元阵列的行方向的行地址信号的变化。只有当行地址转换检测器检测到行地址信号的变化时，才检测冗余位线。

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