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1. 发明授权

US4984207A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4984207A
公开(公告)日：1991-01-08
申请号：US490550
申请日：1990-03-05
申请人： Minoru Tateno , Akira Ide
发明人： Minoru Tateno , Akira Ide
IPC分类号： G11C7/06 , G11C11/416 , G11C11/419
CPC分类号： G11C11/419 , G11C7/062
摘要： A sense amplifier in a semiconductor memory device comprising a differential pair of bipolar transistors whose bases are supplied with read signals appearing on a pair of common data lines pulled up to the side of a positive power source potential, a regulated current circuit which causes a constant current to flow from the common emitters of the pair of bipolar transistors, as well as regulated current circuits which bias the respective bases of the pair of bipolar transistors to the side of a negative power source potential, and a control circuit which switches and controls the respective regulated current circuits in accordance with the select state of the sense amplifier, and also comprising saturation preventive circuits which cause minute currents to flow from the respective bases of the pair of bipolar transistors toward the negative power source potential, so that the bipolar transistors are avoided from falling into saturated states when the regulated current circuits are turned "off," thereby making it possible to reduce the average power consumption of the memory device without delaying the operating speed thereof.
摘要翻译：一种半导体存储器件中的读出放大器，包括一对双极型晶体管，其基极被提供在上升到正电源电位侧的一对公共数据线上出现的读出信号，一个恒定电流电路一对双极晶体管的公共发射极的电流以及将一对双极晶体管的各个基极偏压到负电源电位侧的稳压电路，以及控制电路，其切换和控制根据感测放大器的选择状态的各自的稳压电流电路，并且还包括使微小电流从一对双极晶体管的各个基极流向负电源电位的饱和预防电路，使得双极晶体管避免在调节电流回路时陷入饱和状态 ed“关闭”，从而可以在不延迟其操作速度的情况下降低存储器件的平均功耗。

2. 发明授权

US08765526B2 Method of manufacturing semiconductor device including plural semiconductor chips stacked together 失效
标题翻译：制造半导体器件的方法包括堆叠在一起的多个半导体芯片
公开(公告)号：US08765526B2
公开(公告)日：2014-07-01
申请号：US13333328
申请日：2011-12-21
申请人： Akira Ide
发明人： Akira Ide
IPC分类号： H01L21/50
CPC分类号： H01L24/81 , H01L23/481 , H01L23/544 , H01L24/05 , H01L24/14 , H01L24/16 , H01L24/75 , H01L25/0657 , H01L25/50 , H01L2223/5442 , H01L2223/54426 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05582 , H01L2224/1412 , H01L2224/16145 , H01L2224/17181 , H01L2224/75303 , H01L2224/75702 , H01L2224/75745 , H01L2224/75824 , H01L2224/81132 , H01L2224/81191 , H01L2224/81201 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01051 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/01087 , H01L2924/014 , H01L2924/181 , H01L2224/05552 , H01L2924/00
摘要： Such a method is disclosed that includes preparing first and second semiconductor chips, the first semiconductor chip including a first electrode formed on one surface thereof and a second electrode formed on the other surface thereof so as to overlap the first electrode as viewed from a stacking direction, and the second semiconductor chip including a third electrode formed on one surface thereof and a fourth electrode formed on the other surface thereof so as not to overlap the third electrode as viewed from the stacking direction, and stacking the first and second semiconductor chips in the stacking direction so that the second electrode is connected to the third electrode by using a bonding tool including a concave at a position corresponding to the fourth electrode.
摘要翻译：公开了这样一种方法，其包括制备第一和第二半导体芯片，第一半导体芯片包括在其一个表面上形成的第一电极和形成在其另一个表面上的第二电极，以便从层叠方向观察与第一电极重叠并且第二半导体芯片包括形成在其一个表面上的第三电极和形成在其另一个表面上的第四电极，以便从层叠方向观察不与第三电极重叠，并且将第一和第二半导体芯片堆叠在使得第二电极通过使用在与第四电极对应的位置处包括凹部的接合工具连接到第三电极。

3. 发明授权

US08687444B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08687444B2
公开(公告)日：2014-04-01
申请号：US13200649
申请日：2011-09-28
申请人： Akira Ide , Hiroki Ichikawa
发明人： Akira Ide , Hiroki Ichikawa
IPC分类号： G11C7/00
CPC分类号： G11C29/44 , G11C29/56008 , G11C2029/1208 , G11C2029/5606
摘要： A plurality of memory cells are tested in order. Each time a defective memory cell is detected by the test, error pattern information is updated based on a relative arrangement relationship between a plurality of defective memory cells, and error address information is updated based on the addresses of at least part of the plurality of defective memory cells. According to the present invention, it is possible to significantly reduce the storage capacity of the analysis memory. This allows the implementation of the analysis memory itself in the semiconductor device, in which case external testers need not include the analysis memory.
摘要翻译：按顺序测试多个存储单元。每次通过测试检测到有缺陷的存储单元时，基于多个有缺陷的存储单元之间的相对布置关系来更新错误模式信息，并且基于多个缺陷存储器单元的至少一部分的地址来更新错误地址信息记忆细胞根据本发明，可以显着降低分析存储器的存储容量。这允许在半导体器件中实现分析存储器本身，在这种情况下外部测试器不需要包括分析存储器。

4. 发明授权

US08294449B2 Bandgap reference circuit and method of starting bandgap reference circuit 有权
标题翻译：带隙参考电路及启动带隙参考电路的方法
公开(公告)号：US08294449B2
公开(公告)日：2012-10-23
申请号：US12547156
申请日：2009-08-25
申请人： Akira Ide
发明人： Akira Ide
IPC分类号： G05F3/28
CPC分类号： G05F3/30
摘要： In accordance with a bandgap circuit and a method of starting the bandgap circuit, a start signal is continuously supplied to a differential amplifier circuit to start up the differential amplifier circuit that controls a bandgap core circuit until the differential amplifier circuit has started up, and then the supply of the start signal to the differential amplifier circuit is discontinued after the differential amplifier circuit has started up.
摘要翻译：根据带隙电路和启动带隙电路的方法，将启动信号连续地提供给差分放大器电路，以启动控制带隙核心电路的差分放大器电路，直到差分放大器电路启动，然后在差分放大器电路启动之后，停止向差分放大器电路提供起始信号。

5. 发明申请

US20110211411A1 Semiconductor device, information processing system including same, and controller for controlling semiconductor device 失效
标题翻译：半导体装置，包括它的信息处理系统以及用于控制半导体装置的控制器
公开(公告)号：US20110211411A1
公开(公告)日：2011-09-01
申请号：US12929967
申请日：2011-02-28
申请人： Akira Ide
发明人： Akira Ide
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/06 , G11C5/025 , G11C8/10 , G11C11/4076 , G11C11/408 , G11C11/4087 , H01L2224/16145 , H01L2224/16225 , H01L2924/15311
摘要： To improve the access efficiency of a semiconductor memory that includes a plurality of memory chips. Based on a layer address, a bank address, and a row address received in synchronization with a row command, and a layer address, a bank address, and a column address received in synchronization with a column command, a memory cell selected by the row address and column address in a bank selected by the bank address included in a core chip selected by the chip address is accessed. This can increase the number of banks recognizable to a controller, thereby improving the memory access efficiency of the semiconductor device which includes the plurality of memory chips.
摘要翻译：为了提高包括多个存储器芯片的半导体存储器的访问效率。基于与行命令同步地接收的层地址，存储体地址和行地址以及与列命令同步地接收的层地址，存储体地址和列地址，由行选择的存储单元访问由由芯片地址选择的核心芯片中包含的存储体地址选择的存储体中的地址和列地址。这可以增加控制器可识别的存储体的数量，从而提高包括多个存储器芯片的半导体器件的存储器访问效率。

6. 发明授权

US07750712B2 Timing control circuit, timing generation system, timing control method and semiconductor memory device 有权
标题翻译：定时控制电路，定时生成系统，定时控制方法和半导体存储器件
公开(公告)号：US07750712B2
公开(公告)日：2010-07-06
申请号：US12314207
申请日：2008-12-05
申请人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
发明人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
IPC分类号： H03H11/26
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C19/00 , H03K5/131 , H03K5/14 , H03K2005/00058 , H03K2005/00241
摘要： A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.
摘要翻译：定时控制电路DLY1接收具有周期T1和激活信号ACT的时钟信号CKa，并从m表示非负整数的时钟信号输出延迟m * T1 + tda的精确定时信号FT，并且tda表示模拟延迟元件定时控制电路DLY1包括粗延迟电路CD和精细延迟电路FD。粗延迟电路CD包括用于在接收到激活信号ACT之后对时钟信号CKa的上升沿进行计数的计数器，并输出从时钟信号CKa的上升沿测量的具有延迟m * T1的粗定时信号CT。精细延迟电路FD包括多个模拟延迟元件，并输出从粗定时信号CT测得的具有延迟tda的精细延迟定时信号FT。定时信号延迟的变化减小。

7. 发明申请

US20090086551A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090086551A1
公开(公告)日：2009-04-02
申请号：US12285204
申请日：2008-09-30
申请人： Akira Ide , Yasuhiro Takai , Riichiro Takemura , Tomonori Sekiguchi
发明人： Akira Ide , Yasuhiro Takai , Riichiro Takemura , Tomonori Sekiguchi
IPC分类号： G11C7/00 , G06F11/00 , G06F11/10 , G11C8/00
CPC分类号： G11C11/4093 , G06F11/1004 , G11C7/1006 , G11C7/1012 , G11C8/12
摘要： Disclosed is a semiconductor device in which In case a data group output from a first output pin in a first word configuration is output from the first output pin and a second output pin in a second word configuration, and a data group output from a third output pin in a first word configuration is output from the third output pin and a fourth output pin in a second word configuration, the second output pin is arranged adjacent to the first output pin, and the fourth output pin is arranged adjacent to the third output pin.
摘要翻译：公开了一种半导体器件，其中如果以第一字配置从第一输出引脚输出的数据组以第二字配置从第一输出引脚和第二输出引脚输出，并且从第三输出输出数据组第一字配置中的引脚以第二字配置从第三输出引脚和第四输出引脚输出，第二输出引脚被布置为与第一输出引脚相邻，并且第四输出引脚被布置为与第三输出引脚。

8. 发明授权

US5398318A High speed, low noise output buffer with non-identical pairs of output transistors 失效
标题翻译：具有不相同输出晶体管对的高速，低噪声输出缓冲器
公开(公告)号：US5398318A
公开(公告)日：1995-03-14
申请号：US608370
申请日：1990-11-02
申请人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
发明人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
IPC分类号： G11C11/417 , G11C11/409 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/08 , H03K19/088 , H03K19/0944 , G06F13/00
CPC分类号： H03K19/09448 , H03K17/164 , H03K19/00361
摘要： An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.
摘要翻译：提供了一种改进的缓冲电路装置，其特别适用于半导体集成电路半导体存储器和微处理器。缓冲电路能够切换各种类型的LSI中的大负载，并且具有低噪声和高速电路操作。这通过输出缓冲器电路中的输出晶体管的并联连接，并且通过区分并联连接的输出晶体管之间的操作的起始时间而不使用延迟电路来实现。例如，通过提供具有彼此不同特性的晶体管或具有彼此不同特性的驱动电路，可以实现区分起始时间。电路的另一方面是提供两级预置布置，其在施加输入信号之前将电路的输出节点预设为预定值。

9. 发明授权

US4028392A Isocyanate prepolymers 失效
标题翻译：异氰酸酯预聚物
公开(公告)号：US4028392A
公开(公告)日：1977-06-07
申请号：US579180
申请日：1975-05-20
申请人： Shinsaku Ogawa , Akira Ide , Kazurou Komatsu , Sojiro Matsumoto , Yasushi Kishimoto
发明人： Shinsaku Ogawa , Akira Ide , Kazurou Komatsu , Sojiro Matsumoto , Yasushi Kishimoto
IPC分类号： C08G18/00 , C07C67/00 , C07C239/00 , C07C275/62 , C07C275/70 , C08G18/78 , C08G18/80 , C07C119/042 , C07C119/045 , C07C119/048
CPC分类号： C08G18/7818 , C07C275/70 , C08G18/8045
摘要： An isocyanate prepolymer represented by the formula ##STR1## wherein n is an integer of 1 to 6, R', R" and R'", which may be the same or different, each represents a divalent aliphatic, araliphatic, aromatic or acyclic group which may contain a ##STR2## bond, and R" and R'" may contain a ##STR3## bond, and a process for producing the same.
摘要翻译：由式（I）表示的异氰酸酯预聚物，其中n是1至6的整数，R'，R“和R”'可以相同或不同，表示二价脂族，芳脂族，可以含有键的芳族或非环状基团，R“和R”可以含有键，以及其制备方法。

10. 发明授权

US08468238B2 Computer product, apparatus and method for generating configuration-information for use in monitoring information technology services 有权
标题翻译：用于生成用于监控信息技术服务的配置信息的计算机产品，设备和方法
公开(公告)号：US08468238B2
公开(公告)日：2013-06-18
申请号：US12512822
申请日：2009-07-30
申请人： Kazuyuki Sakai , Akira Ide , Yasushi Kobayashi
发明人： Kazuyuki Sakai , Akira Ide , Yasushi Kobayashi
IPC分类号： G06F15/16 , G06F12/00
CPC分类号： H04L43/0817 , G06F11/3476 , H04L41/0856 , H04L41/0886
摘要： Computer product for generating configuration-information that performs obtaining a first process information operating on a server from each of a plurality of servers constituting an IT system prior to a start of processes in any of the servers, the processes including a process corresponding to an application for an IT service; repeatedly obtaining a second process information from each of the servers through the start to end of the processes performing the application; specifying third process information corresponding to the application by removing the first process information from the second process information; and generating configuration information for monitoring a process condition of the processes, from the third process information, a process name corresponding to the application and identification information of the server where the process corresponds to the process name of the application, the extracted process name being associated with the identification information.
摘要翻译：一种用于生成配置信息的计算机产品，所述配置信息在任何服务器中开始处理之前从构成IT系统的多个服务器中的每一个服务器获得第一处理信息，所述处理包括与应用相对应的处理为IT服务; 通过执行应用的处理的开始到结束，重复从每个服务器获得第二处理信息; 通过从所述第二处理信息中移除所述第一处理信息来指定与所述应用相对应的第三处理信息; 以及生成用于监视所述处理的处理条件的配置信息，从所述第三处理信息，与所述应用程序对应的处理名称和所述处理对应于所述应用的处理名称的所述服务器的识别信息，所提取的进程名称相关联具有识别信息。

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