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1. 发明申请

US20090102524A1 TIMING CONTROL CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：时序控制电路和半导体存储器件
公开(公告)号：US20090102524A1
公开(公告)日：2009-04-23
申请号：US12208978
申请日：2008-09-11
申请人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
发明人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
IPC分类号： H03L7/00
CPC分类号： H03K5/135 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C11/4076 , G11C19/00
摘要： Disclosed is a timing control circuit that receives a first clock having a period T1, a group of second clocks of L different phases spaced apart from each other at substantially equal intervals and selection signals m, n supplied thereto and generates a fine timing signal delayed from the rising edge of the first clock signal by a delay td of approximately td=m·T1+n·(T2/L). The timing control circuit includes a coarse delay circuit and a fine delay circuit. The coarse delay circuit includes a counter for counting a rising edge of the first clock signal after an activate signal is activated and generates a coarse timing signal whose amount of delay from the first clock signal is approximately m·T1. The fine delay circuit comprises L-number of multiphase clock control delay circuits disposed in parallel, delays by n·T2/L the timing of sampling of the coarse timing signal by respective clocks of the group of L-phase second clocks, and takes the OR among the resulting delayed pulses to thereby produce the fine timing signal.
摘要翻译：公开了一种定时控制电路，其接收具有周期T1的第一时钟，以相等间隔彼此间隔开的L个不同相位的一组第二时钟，以及提供给其的选择信号m，n，并产生从第一时钟信号的上升沿大约为td = m.T1 + n。（T2 / L）的延迟td。定时控制电路包括粗延迟电路和精细延迟电路。粗延迟电路包括用于在激活信号被激活之后对第一时钟信号的上升沿进行计数的计数器，并产生其第一时钟信号的延迟量近似为m.T1的粗定时信号。精细延迟电路包括并联设置的L个多相时钟控制延迟电路，延迟n.T2 / L，通过L相第二时钟组的相应时钟对粗略定时信号进行采样的定时，或者产生延迟脉冲，从而产生精细定时信号。

2. 发明授权

US07750712B2 Timing control circuit, timing generation system, timing control method and semiconductor memory device 有权
标题翻译：定时控制电路，定时生成系统，定时控制方法和半导体存储器件
公开(公告)号：US07750712B2
公开(公告)日：2010-07-06
申请号：US12314207
申请日：2008-12-05
申请人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
发明人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
IPC分类号： H03H11/26
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C19/00 , H03K5/131 , H03K5/14 , H03K2005/00058 , H03K2005/00241
摘要： A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.
摘要翻译：定时控制电路DLY1接收具有周期T1和激活信号ACT的时钟信号CKa，并从m表示非负整数的时钟信号输出延迟m * T1 + tda的精确定时信号FT，并且tda表示模拟延迟元件定时控制电路DLY1包括粗延迟电路CD和精细延迟电路FD。粗延迟电路CD包括用于在接收到激活信号ACT之后对时钟信号CKa的上升沿进行计数的计数器，并输出从时钟信号CKa的上升沿测量的具有延迟m * T1的粗定时信号CT。精细延迟电路FD包括多个模拟延迟元件，并输出从粗定时信号CT测得的具有延迟tda的精细延迟定时信号FT。定时信号延迟的变化减小。

3. 发明申请

US20090086551A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090086551A1
公开(公告)日：2009-04-02
申请号：US12285204
申请日：2008-09-30
申请人： Akira Ide , Yasuhiro Takai , Riichiro Takemura , Tomonori Sekiguchi
发明人： Akira Ide , Yasuhiro Takai , Riichiro Takemura , Tomonori Sekiguchi
IPC分类号： G11C7/00 , G06F11/00 , G06F11/10 , G11C8/00
CPC分类号： G11C11/4093 , G06F11/1004 , G11C7/1006 , G11C7/1012 , G11C8/12
摘要： Disclosed is a semiconductor device in which In case a data group output from a first output pin in a first word configuration is output from the first output pin and a second output pin in a second word configuration, and a data group output from a third output pin in a first word configuration is output from the third output pin and a fourth output pin in a second word configuration, the second output pin is arranged adjacent to the first output pin, and the fourth output pin is arranged adjacent to the third output pin.
摘要翻译：公开了一种半导体器件，其中如果以第一字配置从第一输出引脚输出的数据组以第二字配置从第一输出引脚和第二输出引脚输出，并且从第三输出输出数据组第一字配置中的引脚以第二字配置从第三输出引脚和第四输出引脚输出，第二输出引脚被布置为与第一输出引脚相邻，并且第四输出引脚被布置为与第三输出引脚。

4. 发明授权

US07772911B2 Timing control circuit and semiconductor storage device 有权
标题翻译：定时控制电路和半导体存储设备
公开(公告)号：US07772911B2
公开(公告)日：2010-08-10
申请号：US12208978
申请日：2008-09-11
申请人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
发明人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
IPC分类号： G06F1/04
CPC分类号： H03K5/135 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C11/4076 , G11C19/00
摘要： Disclosed is a timing control circuit that receives a first clock having a period T1, a group of second clocks of L different phases spaced apart from each other at substantially equal intervals and selection signals m, n supplied thereto and generates a fine timing signal delayed from the rising edge of the first clock signal by a delay td of approximately td=m·T1+n·(T2/L). The timing control circuit includes a coarse delay circuit and a fine delay circuit. The coarse delay circuit includes a counter for counting a rising edge of the first clock signal after an activate signal is activated and generates a coarse timing signal whose amount of delay from the first clock signal is approximately m·T1. The fine delay circuit comprises L-number of multiphase clock control delay circuits disposed in parallel, delays by n·T2/L the timing of sampling of the coarse timing signal by respective clocks of the group of L-phase second clocks, and takes the OR among the resulting delayed pulses to thereby produce the fine timing signal.
摘要翻译：公开了一种定时控制电路，其接收具有周期T1的第一时钟，以相等间隔彼此间隔开的L个不同相位的一组第二时钟，以及提供给其的选择信号m，n，并产生从第一时钟信号的上升沿大约为td = m·T1 + n·（T2 / L）的延迟td。定时控制电路包括粗延迟电路和精细延迟电路。粗略延迟电路包括用于在激活信号被激活之后对第一时钟信号的上升沿进行计数的计数器，并产生其第一时钟信号的延迟量大约为m·T1的粗略定时信号。精细延迟电路包括L个并联设置的多相时钟控制延迟电路，通过n·T2 / L延迟由L组第二时钟组的相应时钟对粗略定时信号进行采样的定时，或者产生延迟脉冲，从而产生精细定时信号。

5. 发明申请

US20090146716A1 Timing control circuit, timing generation system, timing control method and semiconductor memory device 有权
标题翻译：定时控制电路，定时生成系统，定时控制方法和半导体存储器件
公开(公告)号：US20090146716A1
公开(公告)日：2009-06-11
申请号：US12314207
申请日：2008-12-05
申请人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
发明人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
IPC分类号： H03H11/26
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C19/00 , H03K5/131 , H03K5/14 , H03K2005/00058 , H03K2005/00241
摘要： A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.
摘要翻译：定时控制电路DLY1接收具有周期T1和激活信号ACT的时钟信号CKa，并从m表示非负整数的时钟信号输出延迟m * T1 + tda的精确定时信号FT，并且tda表示模拟延迟元件定时控制电路DLY1包括粗延迟电路CD和精细延迟电路FD。粗延迟电路CD包括用于在接收到激活信号ACT之后对时钟信号CKa的上升沿进行计数的计数器，并输出从时钟信号CKa的上升沿测量的具有延迟m * T1的粗定时信号CT。精细延迟电路FD包括多个模拟延迟元件，并输出从粗定时信号CT测得的具有延迟tda的精细延迟定时信号FT。定时信号延迟的变化减小。

6. 发明申请

US20090180341A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20090180341A1
公开(公告)日：2009-07-16
申请号：US12314860
申请日：2008-12-17
申请人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
发明人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
IPC分类号： G11C7/00 , H03L7/06 , G11C8/18
CPC分类号： G11C7/22 , G11C7/04 , G11C7/1048 , G11C7/12 , G11C7/20 , G11C7/222 , G11C11/4094 , H01L27/0207 , H01L27/108 , H01L27/10897 , H03K5/15066
摘要： Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command. In the operating states, the timing signals are output from the timing generator at a desired timing based on the information stored in the timing register (FIG. 6).
摘要翻译：公开了一种半导体器件，包括第一时钟发生器，其从输入时钟信号产生具有第一周期的第一时钟信号;第二时钟发生器，其从输入时钟信号产生具有第二周期的第二时钟信号;以及定时发生器其接收第一时钟信号，第二时钟信号，来自命令解码器的激活信号和用于从定时寄存器选择延迟时间的选择信号，以产生从激活信号的激活延迟等于等于由选择信号规定的预定数量m的时间等于第一周期的时间和等于由选择信号规定的另一个预设数量n的时间乘以第二周期的时间之和。定时寄存器保存m和n的值。这些值在模式寄存器设置命令时以初始化顺序设置在定时寄存器中。在操作状态下，基于定时寄存器（图6）中存储的信息，定时信号以定时发生器输出。

7. 发明授权

US07973582B2 Timing control circuit and semiconductor storage device 有权
标题翻译：定时控制电路和半导体存储设备
公开(公告)号：US07973582B2
公开(公告)日：2011-07-05
申请号：US12205668
申请日：2008-09-05
申请人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
发明人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
IPC分类号： H03H11/26
CPC分类号： H03K5/15033
摘要： Disclosed is a timing control circuit which receives a first clock having a period T1 and a group of second clocks of L different phases (where L is a positive integer) spaced apart from each other at substantially equal intervals and which generates a fine timing signal delayed from the rising edge of the first clock by a delay td of approximately td=m·T1+n·(T2/L), where m and n are non-negative integers. The timing control circuit has a coarse delay circuit and a fine delay circuit. The coarse delay circuit counts the rising edges of the first clock after an activate signal is activated and generates a coarse timing signal delayed from the first clock by approximately m·T1. The fine delay circuit has a circuit which, after the activate signal is activated, detects a second clock, which has a rising edge that immediately follows the rising edge of the first clock, from among the group of L-phase second clocks. Using the edge-detection information, the fine delay circuit generates a fine timing signal for which the amount of delay from the coarse timing signal is approximately n·(T2/L). The values of m and n can be set by registers.
摘要翻译：公开了一种定时控制电路，其以基本相等的间隔接收具有周期T1和L个不同相位（其中L是正整数）的第二时钟的一组第一时钟，并且产生延迟的精细定时信号从第一时钟的上升沿开始约td = m·T1 + n·（T2 / L）的延迟td，其中m和n是非负整数。定时控制电路具有粗略延迟电路和精细延迟电路。粗略延迟电路在激活信号激活后对第一时钟的上升沿进行计数，并产生从第一个时钟延迟大约m·T1的粗略定时信号。精细延迟电路具有在激活信号被激活之后，从一组L相第二时钟中检测出具有紧跟第一时钟的上升沿的上升沿的第二时钟的电路。利用边缘检测信息，精细延迟电路产生从粗定时信号的延迟量近似为n·（T2 / L）的精细定时信号。 m和n的值可以由寄存器设置。

8. 发明授权

US07903492B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07903492B2
公开(公告)日：2011-03-08
申请号：US12314860
申请日：2008-12-17
申请人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
发明人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/04 , G11C7/1048 , G11C7/12 , G11C7/20 , G11C7/222 , G11C11/4094 , H01L27/0207 , H01L27/108 , H01L27/10897 , H03K5/15066
摘要： Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command. In the operating states, the timing signals are output from the timing generator at a desired timing based on the information stored in the timing register (FIG. 6).
摘要翻译：公开了一种半导体器件，包括第一时钟发生器，其从输入时钟信号产生具有第一周期的第一时钟信号;第二时钟发生器，其从输入时钟信号产生具有第二周期的第二时钟信号;以及定时发生器其接收第一时钟信号，第二时钟信号，来自命令解码器的激活信号和用于从定时寄存器选择延迟时间的选择信号，以产生从激活信号的激活延迟等于等于由选择信号规定的预定数量m的时间等于第一周期的时间和等于由选择信号规定的另一个预设数量n的时间乘以第二周期的时间之和。定时寄存器保存m和n的值。这些值在模式寄存器设置命令时以初始化顺序设置在定时寄存器中。在操作状态下，基于定时寄存器（图6）中存储的信息，定时信号以定时发生器输出。

9. 发明申请

US20120249180A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20120249180A1
公开(公告)日：2012-10-04
申请号：US13429056
申请日：2012-03-23
申请人： Takamasa SUZUKI , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura
发明人： Takamasa SUZUKI , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura
IPC分类号： H03K19/0175
CPC分类号： H03K3/35613
摘要： A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the fifth transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter.
摘要翻译：本文公开了一种可用于电平移位电路的装置。该装置包括分别提供彼此不同的第一，第二和第三电源电压的第一，第二和第三电源线，第一和第二输入端子和输出端子，耦合到第一电源线的输出电路，第一和第二输入端子和输出端子，第一反相器，包括耦合到第一输入端子的输入节点和耦合到第二输入端子的输出节点，在第二和第三功率之间串联耦合到第一反相器的第一晶体管电源线，使第五晶体管不导通以使第一反相器停用;以及控制电路，被配置为在第一反相器停用期间防止输出端子进入电浮动状态。

10. 发明申请

US20110176379A1 SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL ARRAY OF OPEN BIT LINE TYPE AND CONTROL METHOD THEREOF 审中-公开
标题翻译：具有开放式线型存储器单元阵列的半导体存储器件及其控制方法
公开(公告)号：US20110176379A1
公开(公告)日：2011-07-21
申请号：US13008408
申请日：2011-01-18
申请人： Shinichi TAKAYAMA , Akira Kotabe , Kazuo Ono , Tomonori Sekiguchi , Yoshimitsu Yanagawa , Riichiro Takemura
发明人： Shinichi TAKAYAMA , Akira Kotabe , Kazuo Ono , Tomonori Sekiguchi , Yoshimitsu Yanagawa , Riichiro Takemura
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002
摘要： A semiconductor memory device includes: first and second bit lines of an open bit-line system; a sense amplifier that amplifies a potential difference between the first and second bit lines; a pair of first and second local data lines corresponding to the first and second bit lines, respectively; and a write amplifier circuit. The write amplifier circuit changes a potential of the second local data line without changing a potential of the first local data line at a time of writing data for the first bit line, and changes a potential of the first local data line without changing a potential of the second local data line at a time of writing data for the second bit line.
摘要翻译：半导体存储器件包括：开放位线系统的第一和第二位线; 读出放大器，放大第一和第二位线之间的电位差; 对应于第一和第二位线的一对第一和第二本地数据线; 和写放大器电路。写入放大器电路在写入第一位线的数据时改变第二本地数据线的电位而不改变第一本地数据线的电位，并且在不改变第一本地数据线的电位的情况下改变第一本地数据线的电位在第二位线的数据写入时的第二本地数据线。

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