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1. 发明申请

US20150230706A1 VITAL SIGNAL MEASUREMENT DEVICE, AND VITAL SIGN SIGNAL MEASUREMENT SYSTEM 有权
标题翻译： VITAL信号测量装置和VITAL SIGN信号测量系统
公开(公告)号：US20150230706A1
公开(公告)日：2015-08-20
申请号：US14421823
申请日：2012-09-03
申请人： Tatsuo Nakagawa , Tomoyuki Ishii , Akira Kotabe
发明人： Tatsuo Nakagawa , Tomoyuki Ishii , Akira Kotabe
IPC分类号： A61B5/00
CPC分类号： A61B5/0022 , A61B5/0004 , A61B5/0006 , A61B5/0024 , A61B5/02125 , A61B5/0245 , A61B5/04325 , A61B5/7285
摘要： A vital signal measurement system including a plurality of terminals aims to facilitate synchronization of each terminal with respect to other terminals. Each of the plurality of terminals (102) is provided with a first vital signal sensor (201) for measuring a vital signal, a first memory (205) for storing a first data which is based on the vital signal, and a first radio communication unit (206) for communicating with other terminals by radio. The first data is applied with a sequence number corresponding to the first data and the number indicates an order in which the first data is acquired. A first terminal (102b) included in the plurality of terminals performs resetting of the sequence number triggered by the synchronous signal which is received by the first radio communication unit.
摘要翻译：包括多个终端的重要信号测量系统旨在促进每个终端相对于其他终端的同步。多个端子（102）中的每一个设置有用于测量生命信号的第一生命信号传感器（201），用于存储基于重要信号的第一数据的第一存储器（205）和第一无线电通信单元（206），用于通过无线电与其他终端进行通信。第一数据被应用与第一数据对应的序号，数字表示获取第一数据的顺序。包括在多个终端中的第一终端（102b）执行由第一无线电通信单元接收的同步信号触发的序列号的重置。

2. 发明授权

US09099177B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US09099177B2
公开(公告)日：2015-08-04
申请号：US14124725
申请日：2011-06-10
申请人： Yoshitaka Sasago , Masaharu Kinoshita , Akira Kotabe , Takashi Kobayashi
发明人： Yoshitaka Sasago , Masaharu Kinoshita , Akira Kotabe , Takashi Kobayashi
IPC分类号： G11C5/02 , G11C13/00 , H01L27/24 , H01L45/00
CPC分类号： G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C2213/71 , G11C2213/75 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines (2) and bit lines (3) are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically. Such a configuration makes it possible to: form a larger contact at a bundling section (MLC) of wires; and lower a contact resistance in the memory array suitable for miniaturization.
摘要翻译：为了提供适合于小型化并允许接触电阻降低的半导体存储器件，存储器阵列（MA）的布线结构如下形成。也就是说，字线（2）和位线（3）彼此并行扩展，每条字线与另一个字线捆绑，每个位线与另一个位线捆绑，并且两个位线在相应的捆绑的两条字线上垂直形成的电路分离。这样的配置使得可以：在电线的捆扎部分（MLC）处形成较大的接触; 并降低适于小型化的存储器阵列中的接触电阻。

3. 发明申请

US20140218999A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20140218999A1
公开(公告)日：2014-08-07
申请号：US14124725
申请日：2011-06-10
申请人： Yoshitaka Sasago , Masaharu Kinoshita , Akira Kotabe , Takashi Kobayashi
发明人： Yoshitaka Sasago , Masaharu Kinoshita , Akira Kotabe , Takashi Kobayashi
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C2213/71 , G11C2213/75 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines (2) and bit lines (3) are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically. Such a configuration makes it possible to: form a larger contact at a bundling section (MLC) of wires; and lower a contact resistance in the memory array suitable for miniaturization.
摘要翻译：为了提供适合于小型化并允许接触电阻降低的半导体存储器件，存储器阵列（MA）的布线结构如下形成。也就是说，字线（2）和位线（3）彼此并行扩展，每条字线与另一个字线捆绑，每个位线与另一个位线捆绑，并且两个位线在相应的捆绑的两条字线上垂直形成的电路分离。这样的配置使得可以：在电线的捆扎部分（MLC）处形成更大的接触; 并降低适于小型化的存储器阵列中的接触电阻。

4. 发明授权

US08587117B2 Stacked semiconductor chips having circuit element provided with each of the semiconductor chips 失效
标题翻译：具有设置有每个半导体芯片的电路元件的堆叠半导体芯片
公开(公告)号：US08587117B2
公开(公告)日：2013-11-19
申请号：US13455171
申请日：2012-04-25
申请人： Shinichi Takayama , Kazuo Ono , Tomonori Sekiguchi , Akira Kotabe , Yoshimitsu Yanagawa
发明人： Shinichi Takayama , Kazuo Ono , Tomonori Sekiguchi , Akira Kotabe , Yoshimitsu Yanagawa
IPC分类号： H01L23/34
CPC分类号： H01L23/5286 , H01L23/481 , H01L25/0657 , H01L2224/16145 , H01L2225/06544
摘要： A stacked device includes a plurality of semiconductor chips connected to each other by through electrodes. The same number of through electrodes are included in each of paths extending from a first power source terminal through each of circuit elements formed for the semiconductor chips to a second power source terminal.
摘要翻译：堆叠式器件包括通过电极彼此连接的多个半导体芯片。在从第一电源端子通过形成为半导体芯片的电路元件的每一个延伸到第二电源端子的每个路径中包括相同数量的贯通电极。

5. 发明申请

US20110292709A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20110292709A1
公开(公告)日：2011-12-01
申请号：US13117374
申请日：2011-05-27
申请人： Shinichi TAKAYAMA , Akira KOTABE , Kiyoo ITOH , Tomonori SEKIGUCHI
发明人： Shinichi TAKAYAMA , Akira KOTABE , Kiyoo ITOH , Tomonori SEKIGUCHI
IPC分类号： G11C5/06 , G11C7/06
CPC分类号： G11C7/08 , G11C11/4091 , G11C11/4094
摘要： A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.
摘要翻译：半导体器件包括读出放大器电路。读出放大器电路包括执行放大的交叉耦合的第一晶体管和第二晶体管。交叉耦合晶体管的源极分别与第三晶体管和第四晶体管串联连接，并且通过施加到第三和第四晶体管的控制电极的控制电压来控制第三和第四晶体管的电流供应能力。在数据保持期间，保持数据所需的最小子阈值电流根据控制电压流向第三和第四晶体管，并保持位线电位。

6. 发明授权

US08872258B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08872258B2
公开(公告)日：2014-10-28
申请号：US13359453
申请日：2012-01-26
申请人： Soichiro Yoshida , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe
发明人： Soichiro Yoshida , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe
IPC分类号： H01L29/66
CPC分类号： H01L27/10897 , G11C11/4076 , G11C11/4091 , G11C11/4097 , G11C2207/002 , H01L21/823487 , H01L27/0207
摘要： A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate.
摘要翻译：半导体存储器件包括：读出放大器; 多个存储单元阵列; 共享MOS晶体管，其连接/断开读出放大器和存储单元阵列中包含的位线; 以及控制所述共享MOS晶体管的动作的控制电路。作为连接读出放大器和共享MOS晶体管的位线的读出放大器位线的一部分或全部嵌入在半导体衬底中。

7. 发明授权

US08860476B2 Semiconductor device using multi-phase clock signal and information processing system including the same 有权
公开(公告)号：US08860476B2
公开(公告)日：2014-10-14
申请号：US14158253
申请日：2014-01-17
申请人： Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
发明人： Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
IPC分类号： H03L7/00 , H03L7/081 , H03K5/159 , H03K5/13 , H03K5/00
CPC分类号： H03L7/00 , H03K5/133 , H03K5/159 , H03K2005/00032 , H03K2005/00052 , H03L7/0816
摘要： Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.

8. 发明申请

US20130193507A1 SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20130193507A1
公开(公告)日：2013-08-01
申请号：US13359453
申请日：2012-01-26
申请人： Soichiro YOSHIDA , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe
发明人： Soichiro YOSHIDA , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe
IPC分类号： H01L27/088
CPC分类号： H01L27/10897 , G11C11/4076 , G11C11/4091 , G11C11/4097 , G11C2207/002 , H01L21/823487 , H01L27/0207
摘要： A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate.

9. 发明申请

US20130057326A1 SEMICONDUCTOR DEVICE USING MULTI-PHASE CLOCK SIGNAL AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME 有权
标题翻译：使用多相时钟信号的半导体器件和包括其的信息处理系统
公开(公告)号：US20130057326A1
公开(公告)日：2013-03-07
申请号：US13598289
申请日：2012-08-29
申请人： Yoshimitsu YANAGAWA , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
发明人： Yoshimitsu YANAGAWA , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
IPC分类号： H03L7/00 , H03H11/26
CPC分类号： H03L7/00 , H03K5/133 , H03K5/159 , H03K2005/00032 , H03K2005/00052 , H03L7/0816
摘要： Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.
摘要翻译：本文公开了一种包括延迟线的装置，其包括级联的n个延迟电路和将输入时钟信号延迟k个周期的延迟线，以及基于n的至少一部分生成具有不同相位的多相时钟信号的路由电路输出从n个延迟电路输出的时钟信号。 n和k都是大于1的整数，最大公约数为1。

10. 发明申请

US20100073999A1 SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路
公开(公告)号：US20100073999A1
公开(公告)日：2010-03-25
申请号：US12445075
申请日：2006-10-12
申请人： Naoki Kitai , Satoru Hanzawa , Akira Kotabe
发明人： Naoki Kitai , Satoru Hanzawa , Akira Kotabe
IPC分类号： G11C7/00 , G11C11/00 , G11C11/419 , G11C13/00
CPC分类号： G11C11/419 , G11C7/065 , G11C13/0004 , G11C16/28 , G11C2013/0054 , G11C2213/82
摘要： In a readout circuit (RC) which detects a difference between a change that appears on a first signal line (CBL) and a change that appears on a second signal line (CBLdm) according to stored information of each selected memory cell, the first signal line and the second signal line are separated selectively from input nodes of a data latch circuit (DL) through second MOS transistors (MN3 and MN4) and capacitively coupled to the input nodes of the data latch circuit via gates of first MOS transistors (MP1 and MP2) respectively. In this separated state, the first and second signal lines and the input nodes of the data latch circuit are precharged to different voltages, so that the gate-to-source and drain-to-source voltages of the first MOS transistors are controlled by the voltages of the first and second signal lines respectively. Therefore, when the first and second signal lines are varied and the separated state is released upon a read operation, the first MOS transistors start to operate in a saturated region, thereby realizing a high-speed read operation.
摘要翻译：在根据每个所选存储单元的存储信息检测出现在第一信号线（CBL）上的变化与出现在第二信号线（CBLdm）上的变化之间的差异的读出电路（RC）中，第一信号线路和第二信号线通过第二MOS晶体管（MN3和MN4）选择性地从数据锁存电路（DL）的输入节点分离，并且经由第一MOS晶体管（MP1和...的栅极）电容耦合到数据锁存电路的输入节点 MP2）。在这种分离状态下，数据锁存电路的第一和第二信号线和输入节点被预充电到不同的电压，使得第一MOS晶体管的栅极至源极和漏极到源极的电压由分别是第一和第二信号线的电压。因此，当第一和第二信号线变化并且在读取操作时释放分离状态时，第一MOS晶体管开始在饱和区域中工作，从而实现高速读取操作。

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