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    • 7. 发明授权
    • PLL circuit
    • PLL电路
    • US08344770B2
    • 2013-01-01
    • US12929776
    • 2011-02-15
    • Minoru Fukuda
    • Minoru Fukuda
    • H03L7/06
    • H03L7/07H03L7/085
    • A PLL circuit is provided capable of reducing phase noise and facilitating design. In the PLL circuit, a PLL receives a reference frequency and an output from a VC-TCXO, performs a lock operation. In a lock state, a selector selects an output of a first divider that divides the reference frequency. When PLL detects input of reference frequency being lost or an unlock state, the PLL outputs an alarm signal to the selector. When receiving the alarm signal from the PLL, the selector switches from the output of the first divider to an output of a second divider that frequency-divides an output of the VC-TCXO, and outputs the same. Then, a PLL receives an output of the selector and an output of a VCXO and performs a lock operation.
    • 提供了能够减少相位噪声并促进设计的PLL电路。 在PLL电路中,PLL接收参考频率和VC-TCXO的输出,执行锁定操作。 在锁定状态下,选择器选择划分参考频率的第一分频器的输出。 当PLL检测到参考频率丢失或解锁状态的输入时,PLL向选择器输出报警信号。 当从PLL接收到报警信号时,选择器从第一分频器的输出端切换到对VC-TCXO的输出进行分频的第二分频器的输出,并输出。 然后,PLL接收选择器的输出和VCXO的输出,并执行锁定操作。