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1. 发明授权

US6093973A Hard mask for metal patterning 有权
标题翻译：金属图案的硬掩模
公开(公告)号：US6093973A
公开(公告)日：2000-07-25
申请号：US163601
申请日：1998-09-30
申请人： Minh Van Ngo , Bhanwar Singh , Dawn Hopper , Carmen Morales
发明人： Minh Van Ngo , Bhanwar Singh , Dawn Hopper , Carmen Morales
IPC分类号： G03F7/09 , G03F7/11 , H01L23/544
CPC分类号： G03F7/091 , G03F7/11 , Y10S257/915
摘要： An oxide hard mask is formed between a deep ultraviolet photoresist and an anti-reflective coating to prevent interactions with the photoresist, thereby preventing reduction of a critical dimension of a patterned conductive layer. Embodiments include depositing a substantially nitrogen free oxide layer on the anti-reflective coating, such as a silicon oxide derived from tertaethyl orthosilicate by plasma enhanced chemical vapor deposition.
摘要翻译：在深紫外光致抗蚀剂和抗反射涂层之间形成氧化物硬掩模以防止与光致抗蚀剂的相互作用，从而防止图案化导电层的临界尺寸的降低。实施方案包括在抗反射涂层上沉积基本上无氮的氧化物层，例如通过等离子体增强化学气相沉积衍生自原硅酸三乙酯的氧化硅。

2. 发明授权

US06429141B1 Method of manufacturing a semiconductor device with improved line width accuracy 有权
标题翻译：制造具有改善的线宽精度的半导体器件的方法
公开(公告)号：US06429141B1
公开(公告)日：2002-08-06
申请号：US09589105
申请日：2000-06-08
申请人： Minh Van Ngo , Bhanwar Singh , Dawn Hopper , Carmen Morales
发明人： Minh Van Ngo , Bhanwar Singh , Dawn Hopper , Carmen Morales
IPC分类号： H01L21461
CPC分类号： G03F7/091 , G03F7/11 , Y10S257/915
摘要： An oxide hard mask is formed during semiconductor device manufacturing between a deep ultraviolet photoresist and an anti-reflective coating to prevent interactions with the photoresist, thereby preventing reduction of a critical dimension of a patterned conductive layer. Embodiments include a method of manufacturing a semiconductor device comprising depositing a substantially nitrogen free oxide layer on the anti-reflective coating, such as a silicon oxide derived from tertaethyl orthosilicate by plasma enhanced chemical vapor deposition.
摘要翻译：在深紫外光致抗蚀剂和抗反射涂层之间的半导体器件制造期间形成氧化物硬掩模以防止与光致抗蚀剂的相互作用，从而防止图案化导电层的临界尺寸的降低。实施例包括制造半导体器件的方法，包括在抗反射涂层上沉积基本上无氮的氧化物层，例如通过等离子体增强化学气相沉积衍生自原硅酸三乙酯的氧化硅。

3. 发明授权

US07297592B1 Semiconductor memory with data retention liner 有权
标题翻译：具有数据保留衬垫的半导体存储器
公开(公告)号：US07297592B1
公开(公告)日：2007-11-20
申请号：US11195201
申请日：2005-08-01
申请人： Minh Van Ngo , Arvind Halliyal , Tazrien Kamal , Hidehiko Shiraiwa , Rinji Sugino , Dawn Hopper , Pei-Yuan Gao
发明人： Minh Van Ngo , Arvind Halliyal , Tazrien Kamal , Hidehiko Shiraiwa , Rinji Sugino , Dawn Hopper , Pei-Yuan Gao
IPC分类号： H01L21/8247
CPC分类号： H01L21/28282 , H01L21/3185 , H01L27/11568
摘要： A manufacturing method for a dual bit flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer with the depositing performed without using ammonia at an ultra-slow deposition rate. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, high-density data retention liner to reduce charge loss, covers the wordline and the charge-trapping dielectric layer. An interlayer dielectric layer is deposited over the data retention liner.
摘要翻译：一种用于双位闪速存储器的制造方法包括提供半导体衬底和沉积电荷捕获电介质层，其中沉积是以超低沉积速率使用氨而不使用氨。植入第一和第二位线，并存放字线层。硬掩模层沉积在字线层上。光刻胶沉积在字线层上并用于形成硬掩模。去除光致抗蚀剂。使用硬掩模处理字线层以形成字线，并且去除硬掩模。减少氢，高密度数据保持衬垫以减少电荷损失，覆盖字线和电荷捕获电介质层。层间绝缘层沉积在数据保持衬里上。

4. 发明授权

US07071562B2 Interconnects with improved barrier layer adhesion 有权
标题翻译：互连具有改进的阻隔层附着力
公开(公告)号：US07071562B2
公开(公告)日：2006-07-04
申请号：US10662525
申请日：2003-09-16
申请人： Minh Van Ngo , Dawn Hopper
发明人： Minh Van Ngo , Dawn Hopper
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76846 , C23C16/56 , H01L21/76807 , H01L21/76814 , H01L21/76825 , H01L21/76831 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Semiconductor devices comprising interconnect with improved adhesion of barrier layers to dielectric layers are formed by laser thermal annealing exposed surfaces of a dielectric layer in an atmosphere of NH3 and N2, and subsequently depositing Ta to form a composite barrier layer. Embodiments include forming a dual damascene opening in an interlayer dielectric comprising F-containing silicon oxide, such as F-containing silicon oxide derived from F-TEOS, laser thermal annealing the exposed silicon oxide surface in NH3 and N2, depositing Ta and then filling the opening with Cu. Laser thermal annealing in NH3 and N2 depletes the exposed silicon oxide surface of F while forming an N2-rich surface region. Deposited Ta reacts with the N2 in the N2-rich surface region to form a composite barrier layer comprising a graded layer of tantalum nitride and a layer of α-Ta thereon.
摘要翻译：包括具有改善的阻挡层与电介质层的粘附性的互连的半导体器件通过激光热退火在NH 3和N 2的气氛中的电介质层的暴露表面而形成，以及随后沉积Ta以形成复合阻挡层。实施例包括在包含含F的氧化硅的层间电介质中形成双镶嵌开口，例如衍生自F-TEOS的含F的氧化硅，在NH 3中对暴露的氧化硅表面进行激光热退火，以及 N 2，沉积Ta，然后用Cu填充开口。 NH 3和N 2 N中的激光热退火在形成富含N 2的富含表面区域的同时消耗了暴露的F氧化硅表面。沉积的Ta与富含N 2的表面区域中的N 2 N反应形成复合阻挡层，该复合势垒层包括氮化钽的梯度层和其上的α-Ta层。

5. 发明授权

US06645853B1 Interconnects with improved barrier layer adhesion 有权
标题翻译：互连具有改进的阻隔层附着力
公开(公告)号：US06645853B1
公开(公告)日：2003-11-11
申请号：US10001805
申请日：2001-12-05
申请人： Minh Van Ngo , Dawn Hopper
发明人： Minh Van Ngo , Dawn Hopper
IPC分类号： H01L214763
CPC分类号： H01L21/76846 , C23C16/56 , H01L21/76807 , H01L21/76814 , H01L21/76825 , H01L21/76831 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Semiconductor devices comprising interconnect with improved adhesion of barrier layers to dielectric layers are formed by laser thermal annealing exposed surfaces of a dielectric layer in an atmosphere of NH3 and N2, and subsequently depositing Ta to form a composite barrier layer. Embodiments include forming a dual damascene opening in an interlayer dielectric comprising F-containing silicon oxide, such as F-containing silicon oxide derived from F-TEOS, laser thermal annealing the exposed silicon oxide surface in NH3 and N2, depositing Ta and then filling the opening with Cu. Laser thermal annealing in NH3 and N2 depletes the exposed silicon oxide surface of F while forming an N2-rich surface region. Deposited Ta reacts with the N2 in the N2-rich surface region to form a composite barrier layer comprising a graded layer of tantalum nitride and a layer of &agr;-Ta thereon.
摘要翻译：通过在NH 3和N 2的气氛中通过激光热退火介电层的暴露表面，随后沉积Ta形成复合阻挡层，形成包括具有改善的阻挡层与电介质层的粘合性的互连的半导体器件。实施例包括在包含含F的氧化硅的层间电介质中形成双镶嵌开口，例如衍生自F-TEOS的含F的氧化硅，在NH 3和N 2中对暴露的氧化硅表面进行激光热退火，沉积Ta然后填充用Cu打开。 NH3和N2中的激光热退火消耗了暴露的F氧化硅表面，同时形成富氮表面区域。沉积的Ta在富氮的表面区域中与N 2反应以形成包含梯度氮化钽层和其上的α-Ta层的复合势垒层。

6. 发明授权

US06566283B1 Silane treatment of low dielectric constant materials in semiconductor device manufacturing 有权
标题翻译：半导体器件制造中低介电常数材料的硅烷处理
公开(公告)号：US06566283B1
公开(公告)日：2003-05-20
申请号：US10073068
申请日：2002-02-12
申请人： Suzette K. Pangrle , Minh Van Ngo , Dawn Hopper , Lu You
发明人： Suzette K. Pangrle , Minh Van Ngo , Dawn Hopper , Lu You
IPC分类号： H01L2131
CPC分类号： H01L21/76831 , H01L21/31058 , H01L21/76802 , H01L21/76826
摘要： Improved dielectric layers are formed by surface treating the dielectric layer with a silane plasma prior to forming a subsequent layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to a silane plasma produced in a PECVD chamber. A conductive feature is formed by depositing a conformal barrier layer on the low k dielectric including the treated side surfaces of the dielectric and depositing a conductive layer within the trench.
摘要翻译：通过在形成其之后的层之前用硅烷等离子体表面处理电介质层来形成改进的电介质层。实施例包括在低k电介质层中形成沟槽，并通过对电介质进行在PECVD室中产生的硅烷等离子体来修饰沟槽的侧表面。通过在包括电介质处理的侧表面的低k电介质上沉积共形阻挡层并在沟槽内沉积导电层来形成导电特征。

7. 发明授权

US06528432B1 H2-or H2/N2-plasma treatment to prevent organic ILD degradation 有权
标题翻译： H2或H2 / N2等离子体处理以防止有机ILD降解
公开(公告)号：US06528432B1
公开(公告)日：2003-03-04
申请号：US09729455
申请日：2000-12-05
申请人： Minh Van Ngo , Dawn Hopper , Robert A. Huertas
发明人： Minh Van Ngo , Dawn Hopper , Robert A. Huertas
IPC分类号： H01L214763
CPC分类号： H01L23/5329 , H01L21/31058 , H01L21/76826 , H01L21/76829 , H01L2924/0002 , H01L2924/00
摘要： Degradation of organic low-k interlayer dielectrics during fabrication is substantially prevented or significantly reduced by treatment with a H2- or H2/N2-containing plasma. Embodiments include treating a SiCOH, such as Black Diamond®, ILD with an H2 or H2/N2 plasma after deposition, after forming a damascene opening therein and/or after CMP but prior to capping layer deposition.
摘要翻译：通过用含H2或H2 / N2的等离子体处理，可以显着地防止或显着降低制造过程中有机低k层间电介质的退化。实施方案包括在沉积之后，在其中形成镶嵌开口和/或CMP之后，但在覆盖层沉积之前，用H 2或H 2 / N 2等离子体处理SiCOH，例如Black Diamond，ILD。

8. 发明授权

US06436808B1 NH3/N2-plasma treatment to prevent organic ILD degradation 有权
标题翻译： NH3 / N2等离子体处理以防止有机ILD降解
公开(公告)号：US06436808B1
公开(公告)日：2002-08-20
申请号：US09731007
申请日：2000-12-07
申请人： Minh Van Ngo , Dawn Hopper , Jeremy Martin
发明人： Minh Van Ngo , Dawn Hopper , Jeremy Martin
IPC分类号： H01L214763
CPC分类号： H01L21/3105 , H01L21/31633 , H01L21/76826
摘要： Degradation of organic low-k interlayer dielectrics during fabrication is substantially prevented or significantly reduced by treatment with a plasma containing a source of hydrogen and N2. Embodiments include treating a SiCOH, such as Black Diamond®, ILD with a NH3/N2 plasma after deposition, after forming a damascene opening therein and/or after CMP but prior to capping layer deposition.
摘要翻译：通过用含有氢和N 2源的等离子体处理，可以显着地防止或显着降低制造过程中有机低k层间电介质的降解。实施方案包括在沉积之后，在其中形成镶嵌开口和/或CMP之后，但在覆盖层沉积之前，用NH 3 / N 2等离子体处理SiCOH，例如Black Diamond，ILD。

9. 发明授权

US07070911B1 Structure and method for reducing standing waves in a photoresist 失效
标题翻译：用于降低光致抗蚀剂中的驻波的结构和方法
公开(公告)号：US07070911B1
公开(公告)日：2006-07-04
申请号：US10350472
申请日：2003-01-23
申请人： Dawn Hopper , Kouros Ghandehari , Minh Van Ngo
发明人： Dawn Hopper , Kouros Ghandehari , Minh Van Ngo
IPC分类号： G03F7/00
CPC分类号： G03F7/091 , Y10S430/151
摘要： A structure and method for reducing standing waves in a photoresist during manufacturing of a semiconductor is presented. Embodiments of the present invention include a method for reducing standing wave formation in a photoresist during manufacturing a semiconductor device comprising depositing a first anti-reflective coating having an extinction coefficient above a material, and depositing a second anti-reflective coating having an extinction coefficient above the first anti-reflective coating, such that the first anti-reflective coating and the second anti-reflective coating reduce the formation of standing waves in a photoresist during a lithography process.
摘要翻译：提出了一种用于在制造半导体期间降低光致抗蚀剂中的驻波的结构和方法。本发明的实施例包括一种在制造半导体器件期间减少光致抗蚀剂中的驻波形成的方法，包括沉积具有高于材料的消光系数的第一抗反射涂层，以及沉积具有高于上述消光系数的第二抗反射涂层第一抗反射涂层，使得第一抗反射涂层和第二抗反射涂层在光刻工艺期间减少光致抗蚀剂中驻波的形成。

10. 发明授权

US06900121B1 Laser thermal annealing to eliminate oxide voiding 失效
标题翻译：激光热退火以消除氧化物空隙
公开(公告)号：US06900121B1
公开(公告)日：2005-05-31
申请号：US10097015
申请日：2002-03-14
申请人： Minh Van Ngo , Arvind Halliyal , Dawn Hopper
发明人： Minh Van Ngo , Arvind Halliyal , Dawn Hopper
IPC分类号： H01L21/3105 , H01L21/4763 , H01L21/768 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L21/3105 , H01L21/76819 , H01L27/115
摘要： Oxide voiding is eliminated was substantially reduced by laser thermal annealing. Embodiments include fabricating flash memory devices by depositing a BPSG over spaced apart transistors as the first interlayer dielectric with voids formed in gaps between the transistors and laser thermal annealing the BPSG layer in flowing nitrogen to eliminate or substantially reduce the voids by reflowing the BPSG layer.
摘要翻译：通过激光热退火基本上减少了氧化物空隙。实施例包括通过在间隔开的晶体管上沉积BPSG来制造闪速存储器件，作为第一层间电介质，其中形成在晶体管之间的间隙中的空隙，并且在流动的氮气中激发热退火BPSG层，以通过回流BPSG层来消除或基本上减少空隙。

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