专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5716884A Process for fabricating a stacked capacitor 失效
标题翻译：叠层电容器制造工艺
公开(公告)号：US5716884A
公开(公告)日：1998-02-10
申请号：US682403
申请日：1996-07-17
申请人： Chen-Chiu Hsue , Gary Hong , Ming-Tzong Yang
发明人： Chen-Chiu Hsue , Gary Hong , Ming-Tzong Yang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852
摘要： A method for fabricating a capacitor having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multilayer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a polysilicon fin-like bottom capacitor electrode. The remaining multilayer mold is removed and a high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric. The top capacitor electrode is formed by depositing a doped polysilicon layer which also fills the recesses in the bottom electrode forming inter-digitized fin-shaped top and bottom capacitor electrodes and completing a dynamic random access memory (DRAM) cell.
摘要翻译：实现了在具有增加的电容的动态随机存取存储器（DRAM）单元上制造具有鳍状电极的电容器的方法。电容器制造在具有有源器件区域的硅衬底上。器件区域包含一个金属氧化物半导体场效应晶体管（MOSFET），其中一个电容器对准器件区域中与MOSFET的源极/漏极对准并接触。通过在存储电容器区域和凹陷交替层上形成多层绝缘体结构，然后使用该形式作为形成多晶硅鳍状底部电容器电极的模具，电容器增加电容。去除剩余的多层模具，并且在底部电极上沉积高介电常数绝缘体作为电极间电介质。顶部电容器电极通过沉积掺杂多晶硅层而形成，掺杂多晶硅层还填充底部电极中的凹陷，形成数字化的鳍状顶部和底部电容器电极，并完成动态随机存取存储器（DRAM）单元。

2. 发明授权

US5438009A Method of fabrication of MOSFET device with buried bit line 失效
标题翻译：具有掩埋位线的MOSFET器件的制造方法
公开(公告)号：US5438009A
公开(公告)日：1995-08-01
申请号：US100307
申请日：1993-04-02
申请人： Ming-Tzong Yang , Gary Hong
发明人： Ming-Tzong Yang , Gary Hong
IPC分类号： H01L27/108 , H01L27/00 , H01L21/70
CPC分类号： H01L27/10808
摘要： A doped FET DRAM includes a silicon substrate, with a buried bit line in the silicon substrate. A plug extends down through the substrate to the bit line. A source region and a drain region are positioned above the plug in the substrate with one thereof connected to the plug with a layer of gate oxide above the source region and drain region. A gate above the gate oxide is juxtaposed with the source region and drain region. The source is connected to a capacitor formed of two layers of polysilicon separated by a dielectric of an ONO oxide layer.
摘要翻译：掺杂FET DRAM包括在硅衬底中具有掩埋位线的硅衬底。插头通过衬底向下延伸到位线。源极区域和漏极区域位于衬底上的插塞上方，其中一个源极与源极区域和漏极区域上方连接有栅极氧化物层。栅极氧化物上方的栅极与源区和漏区并列。源极连接到由由ONO氧化物层的电介质隔开的两层多晶硅形成的电容器。

3. 发明授权

US5468980A Buried bit line DRAM cell 失效
标题翻译：埋地位线DRAM单元
公开(公告)号：US5468980A
公开(公告)日：1995-11-21
申请号：US334046
申请日：1994-11-04
申请人： Ming-Tzong Yang , Chen-Chiu Hsue , Gary Hong
发明人： Ming-Tzong Yang , Chen-Chiu Hsue , Gary Hong
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76
CPC分类号： H01L27/10852 , H01L27/10808
摘要： Ions of dopant are implanted into predetermined locations in a doped semiconductor substrate in sufficient concentration to form a buried conductor regions. A thick dielectriv layer overlies the surface of the doped substrate. A first polysilicon layer is formed and patterned on the silicon dioxide layer by a mask and etching to form conductor lines, covered by a dielectric. A second polysilicon layer is formed on the second dielectric layer and patterned to form a first capacitor plate. A third dielectric layer is formed on the surface of the second polysilicon layer. A third polysilicon layer is formed on the third dielectric layer and patterned to form a top capacitor plate. A layer of BPSG is deposited upon the third layer of polysilicon.
摘要翻译：掺杂剂的离子以足够的浓度注入掺杂半导体衬底中的预定位置以形成掩埋导体区域。厚的介电层覆盖在掺杂衬底的表面上。通过掩模和蚀刻在二氧化硅层上形成并图案化第一多晶硅层以形成由电介质覆盖的导体线。在第二电介质层上形成第二多晶硅层并构图以形成第一电容器板。在第二多晶硅层的表面上形成第三电介质层。在第三电介质层上形成第三多晶硅层并构图以形成顶部电容器板。一层BPSG沉积在第三层多晶硅上。

4. 发明授权

US5364808A Method of making a buried bit line DRAM cell 失效
标题翻译：埋地位线DRAM单元
公开(公告)号：US5364808A
公开(公告)日：1994-11-15
申请号：US192364
申请日：1994-02-07
申请人： Ming-Tzong Yang , Chen-Chiu Hsue , Gary Hong
发明人： Ming-Tzong Yang , Chen-Chiu Hsue , Gary Hong
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/266
CPC分类号： H01L27/10852 , H01L27/10808
摘要： Ions of dopant are implanted into predetermined locations in a doped semiconductor substrate in sufficient concentration to form a buried conductor regions. A thick dielectric layer overlies the surface of the doped substrate. A first polysilicon layer is formed and patterned on the silicon dioxide layer by a mask and etching to form conductor lines, covered by a dielectric. A second polysilicon layer is formed on the second dielectric layer and patterned to form a first capacitor plate. A third dielectric layer is formed on the surface of the second polysilicon layer. A third polysilicon layer is formed on the third dielectric layer and patterned to form a top capacitor plate. A layer of BPSG is deposited upon the third layer of polysilicon.
摘要翻译：掺杂剂的离子以足够的浓度注入掺杂半导体衬底中的预定位置以形成掩埋导体区域。厚电介质层覆盖在掺杂衬底的表面上。通过掩模和蚀刻在二氧化硅层上形成并图案化第一多晶硅层以形成由电介质覆盖的导体线。在第二电介质层上形成第二多晶硅层并构图以形成第一电容器板。在第二多晶硅层的表面上形成第三电介质层。在第三电介质层上形成第三多晶硅层并构图以形成顶部电容器板。 BPSG层沉积在第三层多晶硅上。

5. 发明授权

US5578857A Double poly high density buried bit line mask ROM 失效
标题翻译：双聚高密度掩埋位线掩模ROM
公开(公告)号：US5578857A
公开(公告)日：1996-11-26
申请号：US349432
申请日：1994-12-05
申请人： Gary Hong , Ming-Tzong Yang , Chen-Chiu Hsue
发明人： Gary Hong , Ming-Tzong Yang , Chen-Chiu Hsue
IPC分类号： H01L21/8246 , H01L29/76
CPC分类号： H01L27/1126
摘要： In accordance with the invention, a double poly process is used to double the memory density of a buried bit line ROM on the same silicon area. In particular the word-line pitch is decreased to increase the cell density in a direction perpendicular to the word lines. The invention uses a self-aligned method for ROM code implantation and a polyplanarization by chemical-mechanical polishing (CMP) to achieve a self aligned double poly word line structure.
摘要翻译：根据本发明，双重多晶法用于将相同硅区上的掩埋位线ROM的存储密度加倍。特别地，减小字线间距以在垂直于字线的方向上增加单元密度。本发明采用自对准方法进行ROM码植入和通过化学机械抛光（CMP）进行多平面化，以实现自对准双多重字线结构。

6. 发明授权

US5449644A Process for contact hole formation using a sacrificial SOG layer 失效
标题翻译：使用牺牲SOG层的接触孔形成方法
公开(公告)号：US5449644A
公开(公告)日：1995-09-12
申请号：US181298
申请日：1994-01-13
申请人： Gary Hong , Cheng H. Huang , Ming-Tzong Yang , Hong-Tsz Pan
发明人： Gary Hong , Cheng H. Huang , Ming-Tzong Yang , Hong-Tsz Pan
IPC分类号： H01L21/768 , H01L21/302
CPC分类号： H01L21/76802 , Y10S148/133
摘要： A new method of forming a contact opening by using a sacrificial spin-on-glass layer is described. A semiconductor substrate is provided wherein the surface of the substrate has an uneven topography. A glasseous layer is deposited over the uneven surface of the substrate and reflowed at low temperature whereby the glasseous layer will have a trench shaped surface over the planned contact opening area. The glasseous layer is covered with a spin-on-glass layer wherein the spin-on-glass planarizes the surface of the substrate. The spin-on-glass layer is baked and then covered with a uniform thickness layer of photoresist. The photoresist layer is exposed and developed to form the desired photoresist mask for the contact opening. The exposed spin-on-glass and glasseous layers are etched away to provide the contact opening to the semiconductor substrate. The photoresist layer is stripped and the sacrificial spin-on-glass layer is removed to complete the formation of the contact opening in the manufacture of the integrated circuit.
摘要翻译：描述了通过使用牺牲旋涂玻璃层形成接触开口的新方法。提供半导体衬底，其中衬底的表面具有不平坦的形貌。在基体的不平坦表面上沉积有胶层，并在低温下回流，由此在层叠的接触开口区域上形成沟槽形表面。玻璃层被旋涂玻璃层覆盖，其中旋涂玻璃将基材的表面平坦化。将旋涂玻璃层烘烤，然后用均匀的厚度的光致抗蚀剂层覆盖。光致抗蚀剂层被曝光和显影以形成用于接触开口的所需光刻胶掩模。暴露的旋涂玻璃和玻璃层被蚀刻掉以提供到半导体衬底的接触开口。剥离光致抗蚀剂层，去除牺牲旋涂玻璃层，以在集成电路的制造中完成接触开口的形成。

7. 发明授权

US5436186A Process for fabricating a stacked capacitor 失效
标题翻译：叠层电容器制造工艺
公开(公告)号：US5436186A
公开(公告)日：1995-07-25
申请号：US231516
申请日：1994-04-22
申请人： Chen-Chiu Hsue , Gary Hong , Ming-Tzong Yang
发明人： Chen-Chiu Hsue , Gary Hong , Ming-Tzong Yang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852
摘要： A method for fabricating a capacitors having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multilayer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a polysilicon fin-like bottom capacitor electrode. The remaining multilayer mold is removed and a high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric. The top capacitor electrode is formed by depositing a doped polysilicon layer which also fills the recesses in the bottom electrode forming an interdigitized fin-shaped top and bottom capacitor electrodes and completing a dynamic random access memory (DRAM) cell.
摘要翻译：实现了在具有增加的电容的动态随机存取存储器（DRAM）单元上制造具有鳍状电极的电容器的方法。电容器制造在具有有源器件区域的硅衬底上。器件区域包含一个金属氧化物半导体场效应晶体管（MOSFET），其中一个电容器对准器件区域中与MOSFET的源极/漏极对准并接触。通过在存储电容器区域和凹陷交替层上形成多层绝缘体结构，然后使用该形式作为形成多晶硅鳍状底部电容器电极的模具，电容器增加电容。去除剩余的多层模具，并且在底部电极上沉积高介电常数绝缘体作为电极间电介质。顶部电容器电极通过沉积掺杂的多晶硅层而形成，掺杂多晶硅层还填充底部电极中的凹部，形成交错的鳍状顶部和底部电容器电极并完成动态随机存取存储器（DRAM）单元。

8. 发明授权

US5393233A Process for fabricating double poly high density buried bit line mask ROM 失效
标题翻译：双重高密度掩埋位线掩模ROM的制造工艺
公开(公告)号：US5393233A
公开(公告)日：1995-02-28
申请号：US92190
申请日：1993-07-14
申请人： Gary Hong , Ming-Tzong Yang , Chen-Chiu Hsue
发明人： Gary Hong , Ming-Tzong Yang , Chen-Chiu Hsue
IPC分类号： H01L21/8246 , H01L21/70
CPC分类号： H01L27/1126
摘要： In accordance with the invention, a double poly process is used to double the memory density of a buried bit line ROM on the same silicon area. In particular the word-line pitch is decreased to increase the cell density in a direction perpendicular to the word lines. The invention uses a self-aligned method for ROM code implantation and a polyplanarization by chemical-mechanical polishing (CMP) to achieve a self aligned double poly word line structure.
摘要翻译：根据本发明，双重多晶法用于将相同硅区上的掩埋位线ROM的存储密度加倍。特别地，减小字线间距以在垂直于字线的方向上增加单元密度。本发明采用自对准方法进行ROM码植入和通过化学机械抛光（CMP）进行多平面化，以实现自对准双多重字线结构。

9. 发明授权

US06750673B1 Method for measuring an effective channel length of a MOSFET 有权
标题翻译：测量MOSFET有效沟道长度的方法
公开(公告)号：US06750673B1
公开(公告)日：2004-06-15
申请号：US10249443
申请日：2003-04-10
申请人： Heng-Sheng Huang , Gary Hong , Shih-Chieh Lin , Yueh-Hsun Lee
发明人： Heng-Sheng Huang , Gary Hong , Shih-Chieh Lin , Yueh-Hsun Lee
IPC分类号： G01R3126
CPC分类号： H01L22/12
摘要： A first compensation factor, a second compensation factor and a third compensation factor are provided to improve a capacitance-voltage (C-V) method for measuring an effective channel length of a metal-oxide-semiconductor field effect transistor (MOSFET), and an overlap length of a gate and a source and a drain of the transistor. The first compensation factor is calculated by measuring two unit length gate capacitances of the transistor. The second compensation factor is calculated by measuring two unit length overlap capacitances of the transistor. The third compensation factor is a ratio of the second compensation factor to the first compensation factor.
摘要翻译：提供第一补偿因子，第二补偿因子和第三补偿因子以改善用于测量金属氧化物半导体场效应晶体管（MOSFET）的有效沟道长度的电容电压（CV）方法，以及重叠长度的晶体管的栅极和源极和漏极。通过测量晶体管的两个单位长度栅极电容来计算第一个补偿因子。通过测量晶体管的两个单位长度重叠电容来计算第二个补偿因子。第三补偿因子是第二补偿因子与第一补偿因子的比率。

10. 发明授权

US06720267B1 Method for forming a cantilever beam model micro-electromechanical system 有权
标题翻译：用于形成悬臂梁模型微机电系统的方法
公开(公告)号：US06720267B1
公开(公告)日：2004-04-13
申请号：US10249149
申请日：2003-03-19
申请人： Anchor Chen , Gary Hong
发明人： Anchor Chen , Gary Hong
IPC分类号： H01L21311
CPC分类号： B81C1/0015 , B81B2201/047
摘要： A cantilever beam type micro-electromechanical system (MEMS) is formed on a substrate. Two first electrodes are formed in a first dielectric layer on the substrate and a waveguide line is formed between the first electrodes. A patterned sacrificial layer and an arm layer are formed on the substrate. Two second electrodes and a second dielectric layer are formed in the arm layer, and an optical grating is formed in the second dielectric layer. Finally, a cap layer is formed on the substrate, and the patterned sacrificial layer is removed.
摘要翻译：在基板上形成悬臂梁型微机电系统（MEMS）。两个第一电极形成在衬底上的第一电介质层中，并且在第一电极之间形成波导线。在基板上形成图案化的牺牲层和臂层。在臂层中形成两个第二电极和第二电介质层，并且在第二电介质层中形成光栅。最后，在衬底上形成覆盖层，去除图案化的牺牲层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式