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1. 发明授权

US5716884A Process for fabricating a stacked capacitor 失效
标题翻译：叠层电容器制造工艺
公开(公告)号：US5716884A
公开(公告)日：1998-02-10
申请号：US682403
申请日：1996-07-17
申请人： Chen-Chiu Hsue , Gary Hong , Ming-Tzong Yang
发明人： Chen-Chiu Hsue , Gary Hong , Ming-Tzong Yang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852
摘要： A method for fabricating a capacitor having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multilayer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a polysilicon fin-like bottom capacitor electrode. The remaining multilayer mold is removed and a high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric. The top capacitor electrode is formed by depositing a doped polysilicon layer which also fills the recesses in the bottom electrode forming inter-digitized fin-shaped top and bottom capacitor electrodes and completing a dynamic random access memory (DRAM) cell.
摘要翻译：实现了在具有增加的电容的动态随机存取存储器（DRAM）单元上制造具有鳍状电极的电容器的方法。电容器制造在具有有源器件区域的硅衬底上。器件区域包含一个金属氧化物半导体场效应晶体管（MOSFET），其中一个电容器对准器件区域中与MOSFET的源极/漏极对准并接触。通过在存储电容器区域和凹陷交替层上形成多层绝缘体结构，然后使用该形式作为形成多晶硅鳍状底部电容器电极的模具，电容器增加电容。去除剩余的多层模具，并且在底部电极上沉积高介电常数绝缘体作为电极间电介质。顶部电容器电极通过沉积掺杂多晶硅层而形成，掺杂多晶硅层还填充底部电极中的凹陷，形成数字化的鳍状顶部和底部电容器电极，并完成动态随机存取存储器（DRAM）单元。

2. 发明授权

US5468980A Buried bit line DRAM cell 失效
标题翻译：埋地位线DRAM单元
公开(公告)号：US5468980A
公开(公告)日：1995-11-21
申请号：US334046
申请日：1994-11-04
申请人： Ming-Tzong Yang , Chen-Chiu Hsue , Gary Hong
发明人： Ming-Tzong Yang , Chen-Chiu Hsue , Gary Hong
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76
CPC分类号： H01L27/10852 , H01L27/10808
摘要： Ions of dopant are implanted into predetermined locations in a doped semiconductor substrate in sufficient concentration to form a buried conductor regions. A thick dielectriv layer overlies the surface of the doped substrate. A first polysilicon layer is formed and patterned on the silicon dioxide layer by a mask and etching to form conductor lines, covered by a dielectric. A second polysilicon layer is formed on the second dielectric layer and patterned to form a first capacitor plate. A third dielectric layer is formed on the surface of the second polysilicon layer. A third polysilicon layer is formed on the third dielectric layer and patterned to form a top capacitor plate. A layer of BPSG is deposited upon the third layer of polysilicon.
摘要翻译：掺杂剂的离子以足够的浓度注入掺杂半导体衬底中的预定位置以形成掩埋导体区域。厚的介电层覆盖在掺杂衬底的表面上。通过掩模和蚀刻在二氧化硅层上形成并图案化第一多晶硅层以形成由电介质覆盖的导体线。在第二电介质层上形成第二多晶硅层并构图以形成第一电容器板。在第二多晶硅层的表面上形成第三电介质层。在第三电介质层上形成第三多晶硅层并构图以形成顶部电容器板。一层BPSG沉积在第三层多晶硅上。

3. 发明授权

US5578857A Double poly high density buried bit line mask ROM 失效
标题翻译：双聚高密度掩埋位线掩模ROM
公开(公告)号：US5578857A
公开(公告)日：1996-11-26
申请号：US349432
申请日：1994-12-05
申请人： Gary Hong , Ming-Tzong Yang , Chen-Chiu Hsue
发明人： Gary Hong , Ming-Tzong Yang , Chen-Chiu Hsue
IPC分类号： H01L21/8246 , H01L29/76
CPC分类号： H01L27/1126
摘要： In accordance with the invention, a double poly process is used to double the memory density of a buried bit line ROM on the same silicon area. In particular the word-line pitch is decreased to increase the cell density in a direction perpendicular to the word lines. The invention uses a self-aligned method for ROM code implantation and a polyplanarization by chemical-mechanical polishing (CMP) to achieve a self aligned double poly word line structure.
摘要翻译：根据本发明，双重多晶法用于将相同硅区上的掩埋位线ROM的存储密度加倍。特别地，减小字线间距以在垂直于字线的方向上增加单元密度。本发明采用自对准方法进行ROM码植入和通过化学机械抛光（CMP）进行多平面化，以实现自对准双多重字线结构。

4. 发明授权

US5436186A Process for fabricating a stacked capacitor 失效
标题翻译：叠层电容器制造工艺
公开(公告)号：US5436186A
公开(公告)日：1995-07-25
申请号：US231516
申请日：1994-04-22
申请人： Chen-Chiu Hsue , Gary Hong , Ming-Tzong Yang
发明人： Chen-Chiu Hsue , Gary Hong , Ming-Tzong Yang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852
摘要： A method for fabricating a capacitors having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multilayer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a polysilicon fin-like bottom capacitor electrode. The remaining multilayer mold is removed and a high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric. The top capacitor electrode is formed by depositing a doped polysilicon layer which also fills the recesses in the bottom electrode forming an interdigitized fin-shaped top and bottom capacitor electrodes and completing a dynamic random access memory (DRAM) cell.
摘要翻译：实现了在具有增加的电容的动态随机存取存储器（DRAM）单元上制造具有鳍状电极的电容器的方法。电容器制造在具有有源器件区域的硅衬底上。器件区域包含一个金属氧化物半导体场效应晶体管（MOSFET），其中一个电容器对准器件区域中与MOSFET的源极/漏极对准并接触。通过在存储电容器区域和凹陷交替层上形成多层绝缘体结构，然后使用该形式作为形成多晶硅鳍状底部电容器电极的模具，电容器增加电容。去除剩余的多层模具，并且在底部电极上沉积高介电常数绝缘体作为电极间电介质。顶部电容器电极通过沉积掺杂的多晶硅层而形成，掺杂多晶硅层还填充底部电极中的凹部，形成交错的鳍状顶部和底部电容器电极并完成动态随机存取存储器（DRAM）单元。

5. 发明授权

US5393233A Process for fabricating double poly high density buried bit line mask ROM 失效
标题翻译：双重高密度掩埋位线掩模ROM的制造工艺
公开(公告)号：US5393233A
公开(公告)日：1995-02-28
申请号：US92190
申请日：1993-07-14
申请人： Gary Hong , Ming-Tzong Yang , Chen-Chiu Hsue
发明人： Gary Hong , Ming-Tzong Yang , Chen-Chiu Hsue
IPC分类号： H01L21/8246 , H01L21/70
CPC分类号： H01L27/1126
摘要： In accordance with the invention, a double poly process is used to double the memory density of a buried bit line ROM on the same silicon area. In particular the word-line pitch is decreased to increase the cell density in a direction perpendicular to the word lines. The invention uses a self-aligned method for ROM code implantation and a polyplanarization by chemical-mechanical polishing (CMP) to achieve a self aligned double poly word line structure.
摘要翻译：根据本发明，双重多晶法用于将相同硅区上的掩埋位线ROM的存储密度加倍。特别地，减小字线间距以在垂直于字线的方向上增加单元密度。本发明采用自对准方法进行ROM码植入和通过化学机械抛光（CMP）进行多平面化，以实现自对准双多重字线结构。

6. 发明授权

US5364808A Method of making a buried bit line DRAM cell 失效
标题翻译：埋地位线DRAM单元
公开(公告)号：US5364808A
公开(公告)日：1994-11-15
申请号：US192364
申请日：1994-02-07
申请人： Ming-Tzong Yang , Chen-Chiu Hsue , Gary Hong
发明人： Ming-Tzong Yang , Chen-Chiu Hsue , Gary Hong
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/266
CPC分类号： H01L27/10852 , H01L27/10808
摘要： Ions of dopant are implanted into predetermined locations in a doped semiconductor substrate in sufficient concentration to form a buried conductor regions. A thick dielectric layer overlies the surface of the doped substrate. A first polysilicon layer is formed and patterned on the silicon dioxide layer by a mask and etching to form conductor lines, covered by a dielectric. A second polysilicon layer is formed on the second dielectric layer and patterned to form a first capacitor plate. A third dielectric layer is formed on the surface of the second polysilicon layer. A third polysilicon layer is formed on the third dielectric layer and patterned to form a top capacitor plate. A layer of BPSG is deposited upon the third layer of polysilicon.
摘要翻译：掺杂剂的离子以足够的浓度注入掺杂半导体衬底中的预定位置以形成掩埋导体区域。厚电介质层覆盖在掺杂衬底的表面上。通过掩模和蚀刻在二氧化硅层上形成并图案化第一多晶硅层以形成由电介质覆盖的导体线。在第二电介质层上形成第二多晶硅层并构图以形成第一电容器板。在第二多晶硅层的表面上形成第三电介质层。在第三电介质层上形成第三多晶硅层并构图以形成顶部电容器板。 BPSG层沉积在第三层多晶硅上。

7. 发明授权

US5418176A Process for producing memory devices having narrow buried N+ lines 失效
标题翻译：具有窄掩埋N +线的存储器件的制造方法
公开(公告)号：US5418176A
公开(公告)日：1995-05-23
申请号：US197748
申请日：1994-02-17
申请人： Ming-Tzong Yang , Cheng-Han Huang , Chen-Chiu Hsue
发明人： Ming-Tzong Yang , Cheng-Han Huang , Chen-Chiu Hsue
IPC分类号： H01L21/8246
CPC分类号： H01L27/1122
摘要： A process of fabricating a read only memory device (ROM) wherein the buried N+lines have desirable well defined very narrow widths and are closely spaced. In the process, an insulating layer is deposited on the substrate. Openings for the buried N+lines having vertical sidewalls are formed through the insulating layer. Spacer layers are formed on the vertical sidewalls of the openings. Impurities are implanted through the openings. The insulating layers is removed and the substrate is oxidized to form silicon oxide insulation strips over the buried N+implanted regions. Next, the read only memory (ROM) device is completed by fabricating floating gates and overlying control gates between the buried N+lines interconnected by a conductive lines that are orthogonal to the buried N+buried lines.
摘要翻译：一种制造只读存储器件（ROM）的工艺，其中掩埋的N +线具有期望的良好定义非常窄的宽度并且紧密间隔开。在该过程中，绝缘层沉积在衬底上。通过绝缘层形成具有垂直侧壁的埋入N +线的开口。间隔层形成在开口的垂直侧壁上。通过开口植入杂质。绝缘层被去除并且衬底被氧化以在掩埋的N +注入区域上形成氧化硅绝缘条。接下来，通过在与埋置的N +掩埋线正交的导线相互连接的掩埋N +线之间制造浮动栅极和覆盖控制栅极来完成只读存储器（ROM）器件。

8. 发明授权

US5380673A Dram capacitor structure 失效
标题翻译：戏剧电容器结构
公开(公告)号：US5380673A
公开(公告)日：1995-01-10
申请号：US239130
申请日：1994-05-06
申请人： Ming-Tzong Yang , Chen-Chiu Hsue , Anchor Chen
发明人： Ming-Tzong Yang , Chen-Chiu Hsue , Anchor Chen
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/92
摘要： A new structure and method for fabricating a stacked capacitor with increased capacitance and which is more manufacturable was accomplished. The stacked capacitor is part of a dynamic random access memory (DRAM) cell for storing charge on the capacitor and together with a field effect transistor (MOSFET) make up the individual DRAM storage cells on a DRAM chip. Fabricating this improved stacked capacitor involves using an additional electrically conducting layer in the polysilicon layer of the bottom electrode. For example, this layer can be composed from materials in the metal nitride group having high conductivity. One preferred choice being titanium nitride (TiN). The bottom electrode is formed by depositing and patterning a thin layer of polysilicon and a thin layer of the electrically conducting layer and then depositing an upper layer of polysilicon from which vertical sidewalls are formed. The conducting layer provides an etch end point for accurately etching to the correct depth. This provided for a repeatable and more manufacturable process. The stacked capacitor is then completed by depositing a high dielectric constant insulator layer over the bottom electrode and forming a top capacitor electrode to complete the stacked capacitor. The bottom electrode contacts one source/drain contacts of the MOSFET and the bit line contacts the other source/drain contact completing the improved DRAM cell.
摘要翻译：实现了一种用于制造具有增加的电容并且更可制造的层叠电容器的新结构和方法。堆叠电容器是用于在电容器上存储电荷并与场效应晶体管（MOSFET）一起构成DRAM芯片上的各个DRAM存储单元的动态随机存取存储器（DRAM）单元的一部分。制造这种改进的堆叠电容器包括在底部电极的多晶硅层中使用附加的导电层。例如，该层可以由具有高导电性的金属氮化物基团中的材料构成。一种优选的选择是氮化钛（TiN）。底部电极通过沉积和图案化多晶硅薄层和导电层的薄层而形成，然后沉积形成垂直侧壁的多晶硅上层。导电层提供蚀刻终点以准确地蚀刻到正确的深度。这提供了可重复和更可制造的过程。然后通过在底部电极上沉积高介电常数绝缘体层并形成顶部电容器电极以完成堆叠的电容器来完成叠层电容器。底部电极接触MOSFET的一个源极/漏极触点，并且位线接触另一个源极/漏极触点，从而完成改进的DRAM单元。

9. 发明授权

US5661047A Method for forming bipolar ROM device 失效
标题翻译：形成双极型ROM器件的方法
公开(公告)号：US5661047A
公开(公告)日：1997-08-26
申请号：US318213
申请日：1994-10-05
申请人： Chen-Chiu Hsue , Ming-Tzong Yang
发明人： Chen-Chiu Hsue , Ming-Tzong Yang
IPC分类号： H01L21/8229 , H01L21/265
CPC分类号： H01L21/8229
摘要： A method of forming bipolar ROM device on a semiconductor substrate comprises forming a collector region by doping with a dopant of a first polarity, forming an array of common base regions by doping with a dopant of an opposite polarity, forming a plurality of emitter regions selectively in the base regions by doping with a dopant of first polarity and diffusing the dopant into the emitter regions from doped conductors, which conductors are formed as an array of conductors disposed orthogonally relative to the array of common base elements. The conductors are connected to emitter regions traversed thereby and are isolated from other regions by dielectric layers selectively formed over the other regions to prevent diffusion of dopant therethrough to prevent formation of such emitter regions.
摘要翻译：在半导体衬底上形成双极型ROM器件的方法包括通过掺杂第一极性的掺杂剂形成集电极区域，通过掺杂相反极性的掺杂剂形成公共基极区域阵列，从而选择性地形成多个发射极区域通过掺杂第一极性的掺杂剂在基极区域中，并且将掺杂剂从掺杂导体扩散到发射极区域，该导体形成为相对于共同基极元件阵列正交配置的导体阵列。导体连接到由此穿过的发射极区域，并且通过在其它区域上有选择地形成的电介质层与其它区域隔离，以防止掺杂剂扩散通过其中以防止形成这种发射极区域。

10. 发明授权

US5480822A Method of manufacture of semiconductor memory device with multiple, orthogonally disposed conductors 失效
标题翻译：具有多个正交布置的导体的半导体存储器件的制造方法
公开(公告)号：US5480822A
公开(公告)日：1996-01-02
申请号：US345127
申请日：1994-11-28
申请人： Chen-Chiu Hsue , Ming-Tzong Yang
发明人： Chen-Chiu Hsue , Ming-Tzong Yang
IPC分类号： H01L21/768 , H01L23/528 , H01L21/265
CPC分类号： H01L23/5283 , H01L21/768 , H01L2924/0002
摘要： In accordance with this invention, a method of manufacture of a semiconductor memory device comprises the following steps: forming field oxide structures on a semiconductor substrate, forming a gate oxide layer on exposed surfaces of the substrate, forming a first word line layer on the device, patterning the first word line layer by forming a first patterned mask mask with a first set of openings therein and etching the first word line layer through the openings in the first mask to form conductor lines, forming a first dielectric layer on the surface of the first word line layer on the device, forming a second word line layer on the first dielectric layer, patterning the second word line layer by forming a second patterning mask with a second set of openings therein and etching portions of the second word line layer therethrough, h)forming a second dielectric layer on the surface of the second word line layer on the device, and implanting ions of dopant into predetermined locations into the semiconductor substrate of the device, the dopant being of sufficient concentration to form a doped region therein.
摘要翻译：根据本发明，半导体存储器件的制造方法包括以下步骤：在半导体衬底上形成场氧化物结构，在衬底的暴露表面上形成栅氧化层，在器件上形成第一字线层通过在其中形成具有第一组开口的第一图案化掩模掩模来形成第一字线层，并通过第一掩模中的开口蚀刻第一字线层以形成导体线，在第一掩模掩模的表面上形成第一介电层第一字线层，在第一介电层上形成第二字线层，通过形成具有第二组开口的第二图案掩模和第二字线层的蚀刻部分来图形化第二字线层， h）在所述器件上的所述第二字线层的表面上形成第二电介质层，以及将掺杂剂的离子注入预定位置i n到器件的半导体衬底，掺杂剂具有足够的浓度以在其中形成掺杂区域。

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