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1. 发明申请

US20050289317A1 METHOD AND RELATED APPARATUS FOR ACCESSING MEMORY 有权
标题翻译：用于访问存储器的方法和相关装置
公开(公告)号：US20050289317A1
公开(公告)日：2005-12-29
申请号：US10906748
申请日：2005-03-04
申请人： Ming-Shi Liou , Bowei Hsieh , Jiin Lai
发明人： Ming-Shi Liou , Bowei Hsieh , Jiin Lai
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1684 , G11C2207/2281
摘要： A method for utilizing the multi-channel transmission bandwidth in an asymmetrically arranged memory is provides. The present invention defines symmetrically arranged parts of the memory ranks of the memory as a virtual ranks. If data is stored in symmetrically arranged memory ranks of the memory, channels corresponding to the symmetrically arranged memory ranks could be simultaneously utilized to transfer data. If data is stored in an asymmetrically arranged memory rank of the memory, the channel corresponding to the asymmetrically arranged memory rank could only be utilized to transfer data.
摘要翻译：提供了一种在不对称布置的存储器中利用多通道传输带宽的方法。本发明将存储器的存储器级别的对称布置部分定义为虚拟等级。如果数据存储在存储器的对称布置的存储器级中，则对应于对称排列的存储器级别的通道可以同时用于传送数据。如果数据被存储在存储器的不对称排列的存储器级中，则对应于不对称布置的存储器级的通道只能用于传送数据。

2. 发明授权

US07779215B2 Method and related apparatus for accessing memory 有权
标题翻译：用于访问存储器的方法和相关装置
公开(公告)号：US07779215B2
公开(公告)日：2010-08-17
申请号：US10906748
申请日：2005-03-04
申请人： Ming-Shi Liou , Bowei Hsieh , Jiin Lai
发明人： Ming-Shi Liou , Bowei Hsieh , Jiin Lai
IPC分类号： G06F12/06
CPC分类号： G06F13/1684 , G11C2207/2281
摘要： A method for utilizing the multi-channel transmission bandwidth in an asymmetrically arranged memory is provides. The present invention defines symmetrically arranged parts of the memory ranks of the memory as a virtual ranks. If data is stored in symmetrically arranged memory ranks of the memory, channels corresponding to the symmetrically arranged memory ranks could be simultaneously utilized to transfer data. If data is stored in an asymmetrically arranged memory rank of the memory, the channel corresponding to the asymmetrically arranged memory rank could only be utilized to transfer data.
摘要翻译：提供了一种在不对称布置的存储器中利用多通道传输带宽的方法。本发明将存储器的存储器级别的对称布置部分定义为虚拟等级。如果数据存储在存储器的对称布置的存储器级中，则对应于对称排列的存储器级别的通道可以同时用于传送数据。如果数据被存储在存储器的不对称排列的存储器级中，则对应于不对称布置的存储器级的通道只能用于传送数据。

3. 发明申请

US20060080565A1 METHOD AND RELATED APPARATUS FOR ADJUSTING TIMING OF MEMORY SIGNALS 有权
标题翻译：用于调整记忆信号时序的方法和相关装置
公开(公告)号：US20060080565A1
公开(公告)日：2006-04-13
申请号：US10905903
申请日：2005-01-26
申请人： Bowei Hsieh , Ming-Shi Liou
发明人： Bowei Hsieh , Ming-Shi Liou
IPC分类号： G06F1/12
CPC分类号： G06F1/10
摘要： A method and related apparatus for adjusting/calibrating timing of memory signals. In a preferred embodiment of the invention, reference signals of the same frequency and different phase are generated by a phase-lock loop. These reference signals are used to trigger sampling of signals for generating signals of different timing/delay; then timing/delay of memory signals, such as clock, command, data and data strobe, can be adjusted and calibrated. In this way, the invention can avoid the use of delay lines while adjusting/calibrating memory signals, so as to reduce the negative effects of characteristics shift and variation of delay lines.
摘要翻译：一种用于调整/校准存储信号定时的方法和相关装置。在本发明的优选实施例中，相位频率和不同相位的参考信号由锁相环产生。这些参考信号用于触发用于产生不同定时/延迟信号的信号采样; 那么可以调整和校准诸如时钟，命令，数据和数据选通的存储器信号的定时/延迟。以这种方式，本发明可以避免在调整/校准存储信号的同时使用延迟线，以减少延迟线的特性偏移和变化的负面影响。

4. 发明授权

US07418617B2 Apparatus for adjusting timing of memory signals 有权
标题翻译：用于调整存储信号定时的装置
公开(公告)号：US07418617B2
公开(公告)日：2008-08-26
申请号：US11749162
申请日：2007-05-16
申请人： Bowei Hsieh , Ming-Shi Liou
发明人： Bowei Hsieh , Ming-Shi Liou
IPC分类号： G06F1/04 , G06F1/12
CPC分类号： G06F1/10
摘要： An adjusting circuit for adjusting timings of memory signals of a computer system is provided. The adjusting circuit includes: a clock generator for generating a plurality of reference signals, all having the same frequency but different phase; a multiplexing unit connected to the clock generator for receiving the reference signals, wherein the multiplexing unit selects a first reference signal according to a selecting signal; and an adjusting unit connected to the multiplexing unit for receiving a signal and delaying to output the signal according to the first reference signal selected by the multiplexing unit.
摘要翻译：提供了一种用于调整计算机系统的存储信号的定时的调整电路。调整电路包括：时钟发生器，用于产生多个参考信号，全部具有相同频率但相位相同; 连接到时钟发生器的多路复用单元，用于接收参考信号，其中复用单元根据选择信号选择第一参考信号; 以及调整单元，连接到多路复用单元，用于接收信号并根据由多路复用单元选择的第一参考信号延迟输出信号。

5. 发明申请

US20070214378A1 Apparatus for Adjusting Timing of Memory Signals 有权
标题翻译：用于调整存储信号时序的装置
公开(公告)号：US20070214378A1
公开(公告)日：2007-09-13
申请号：US11749162
申请日：2007-05-16
申请人： Bowei Hsieh , Ming-Shi Liou
发明人： Bowei Hsieh , Ming-Shi Liou
IPC分类号： G06F1/12
CPC分类号： G06F1/10
摘要： An adjusting circuit for adjusting timings of memory signals of a computer system is provided. The adjusting circuit includes: a clock generator for generating a plurality of reference signals, all having the same frequency but different phase; a multiplexing unit connected to the clock generator for receiving the reference signals, wherein the multiplexing unit selects a first reference signal according to a selecting signal; and an adjusting unit connected to the multiplexing unit for receiving a signal and delaying to output the signal according to the first reference signal selected by the multiplexing unit.
摘要翻译：提供了一种用于调整计算机系统的存储信号的定时的调整电路。调整电路包括：时钟发生器，用于产生多个参考信号，全部具有相同频率但相位相同; 连接到时钟发生器的多路复用单元，用于接收参考信号，其中复用单元根据选择信号选择第一参考信号; 以及调整单元，连接到多路复用单元，用于接收信号并根据由多路复用单元选择的第一参考信号延迟输出信号。

6. 发明授权

US07444535B2 Method and related apparatus for adjusting timing of memory signals 有权
标题翻译：用于调整存储器信号定时的方法和相关装置
公开(公告)号：US07444535B2
公开(公告)日：2008-10-28
申请号：US10905903
申请日：2005-01-26
申请人： Bowei Hsieh , Ming-Shi Liou
发明人： Bowei Hsieh , Ming-Shi Liou
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A method and related apparatus for adjusting/calibrating timing of memory signals. In a preferred embodiment of the invention, reference signals of the same frequency and different phase are generated by a phase-lock loop. These reference signals are used to trigger sampling of signals for generating signals of different timing/delay; then timing/delay of memory signals, such as clock, command, data and data strobe, can be adjusted and calibrated. In this way, the invention can avoid the use of delay lines while adjusting/calibrating memory signals, so as to reduce the negative effects of characteristics shift and variation of delay lines.
摘要翻译：一种用于调整/校准存储信号定时的方法和相关装置。在本发明的优选实施例中，相位频率和不同相位的参考信号由锁相环产生。这些参考信号用于触发用于产生不同定时/延迟信号的信号采样; 那么可以调整和校准诸如时钟，命令，数据和数据选通的存储器信号的定时/延迟。以这种方式，本发明可以避免在调整/校准存储信号的同时使用延迟线，以减少延迟线的特性偏移和变化的负面影响。

7. 发明授权

US07853843B2 Method and system for testing chips 有权
标题翻译：测试芯片的方法和系统
公开(公告)号：US07853843B2
公开(公告)日：2010-12-14
申请号：US11668440
申请日：2007-01-29
申请人： Hsiang-Che Hsu , Bowei Hsieh
发明人： Hsiang-Che Hsu , Bowei Hsieh
IPC分类号： G01R31/28
CPC分类号： G01R31/31715 , G01R31/31716
摘要： Method and related system for testing a chip with high speed I/O functions are provided. The testing method of a chip includes the steps of: receiving a testing signal from a low speed bus; then transmitting the testing signal according to a transmission control signal; then receiving the testing signal according to a receiving control signal; and comparing the transmitted testing signal and the received testing signal to identify the I/O functions of the chip.
摘要翻译：提供了用于测试具有高速I / O功能的芯片的方法和相关系统。芯片的测试方法包括以下步骤：从低速总线接收测试信号; 然后根据发送控制信号发送测试信号; 然后根据接收控制信号接收测试信号; 并将发送的测试信号与接收的测试信号进行比较，以识别芯片的I / O功能。

8. 发明申请

US20080104463A1 METHOD AND SYSTEM FOR TESTING CHIPS 有权
标题翻译：测试方法和系统
公开(公告)号：US20080104463A1
公开(公告)日：2008-05-01
申请号：US11668440
申请日：2007-01-29
申请人： Hsiang-Che Hsu , Bowei Hsieh
发明人： Hsiang-Che Hsu , Bowei Hsieh
IPC分类号： G01R31/28
CPC分类号： G01R31/31715 , G01R31/31716
摘要： Method and related system for testing a chip with high speed I/O functions are provided. The testing method of a chip includes the steps of: receiving a testing signal from a low speed bus; then transmitting the testing signal according to a transmission control signal; then receiving the testing signal according to a receiving control signal; and comparing the transmitted testing signal and the received testing signal to identify the I/O functions of the chip.
摘要翻译：提供了用于测试具有高速I / O功能的芯片的方法和相关系统。芯片的测试方法包括以下步骤：从低速总线接收测试信号; 然后根据发送控制信号发送测试信号; 然后根据接收控制信号接收测试信号; 并将发送的测试信号与接收的测试信号进行比较，以识别芯片的I / O功能。

9. 发明授权

US08694839B2 Method and system for testing chips 有权
标题翻译：测试芯片的方法和系统
公开(公告)号：US08694839B2
公开(公告)日：2014-04-08
申请号：US12938392
申请日：2010-11-03
申请人： Hsiang-Che Hsu , Bowei Hsieh
发明人： Hsiang-Che Hsu , Bowei Hsieh
IPC分类号： G11C29/00 , G06F11/00 , G01R31/08 , G08C15/00 , H04J1/16
CPC分类号： G01R31/31715 , G01R31/31716
摘要： A chip operating method is provided which includes enabling a transmission mechanism or a receiving mechanism of the chip while normally operating the chip. The method further includes enabling both of the transmission mechanism and the receiving mechanism of the chip while testing the chip.
摘要翻译：提供一种芯片操作方法，其包括在正常操作芯片的同时实现芯片的传输机制或接收机制。该方法还包括在测试芯片时实现芯片的传输机制和接收机制两者。

10. 发明申请

US20110047420A1 METHOD AND SYSTEM FOR TESTING CHIPS 有权
标题翻译：测试方法和系统
公开(公告)号：US20110047420A1
公开(公告)日：2011-02-24
申请号：US12938392
申请日：2010-11-03
申请人： Hsiang-Che Hsu , Bowei Hsieh
发明人： Hsiang-Che Hsu , Bowei Hsieh
IPC分类号： G06F11/263
CPC分类号： G01R31/31715 , G01R31/31716
摘要： A chip operating method is provided which includes enabling a transmission mechanism or a receiving mechanism of the chip while normally operating the chip. The method further includes enabling both of the transmission mechanism and the receiving mechanism of the chip while testing the chip.
摘要翻译：提供一种芯片操作方法，其包括在正常操作芯片的同时实现芯片的传输机制或接收机制。该方法还包括在测试芯片时实现芯片的传输机制和接收机制两者。

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