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1. 发明授权

US08610488B2 3X input voltage tolerant device and circuit 有权
标题翻译： 3X输入电压容差器件和电路
公开(公告)号：US08610488B2
公开(公告)日：2013-12-17
申请号：US13349152
申请日：2012-01-12
申请人： Ming-Hsin Yu , Guang-Cheng Wang
发明人： Ming-Hsin Yu , Guang-Cheng Wang
IPC分类号： H03K17/08 , H03K17/687 , H03K19/094
CPC分类号： H03K19/018507 , H01L27/0266
摘要： A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltages at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages.
摘要翻译：耦合到输入/输出焊盘的耐压输入/输出电路，并且能够支持大约两倍的工作电压的电压过驱动操作，并且具有大约是工作电压的三倍的输入容差。该电路包括上拉驱动器，P屏蔽，N屏蔽，下拉驱动器和交叉控制电路。上拉驱动器耦合到电源。 P屏蔽具有N阱并且在节点C处耦合到上拉驱动器，并且耦合到输入/输出焊盘。 N屏蔽也耦合到输入/输出板。下拉驱动器在节点A处的接地和N屏蔽之间耦合。交叉控制电路被配置为检测节点A，节点C和输入/输出板上的电压。交叉控制电路被配置为基于检测到的电压将控制信号输出到P屏蔽和N屏蔽。

2. 发明申请

US20130181768A1 3X INPUT VOLTAGE TOLERANT DEVICE AND CIRCUIT 有权
标题翻译： 3X输入电压容差器件和电路
公开(公告)号：US20130181768A1
公开(公告)日：2013-07-18
申请号：US13349152
申请日：2012-01-12
申请人： Ming-Hsin YU , Guang-Cheng Wang
发明人： Ming-Hsin YU , Guang-Cheng Wang
IPC分类号： G05F3/02
CPC分类号： H03K19/018507 , H01L27/0266
摘要： A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltage at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages.
摘要翻译：耦合到输入/输出焊盘的耐压输入/输出电路，并且能够支持大约两倍的工作电压的电压过驱动操作，并且具有大约是工作电压的三倍的输入容差。该电路包括上拉驱动器，P屏蔽，N屏蔽，下拉驱动器和交叉控制电路。上拉驱动器耦合到电源。 P屏蔽具有N阱并且在节点C处耦合到上拉驱动器，并且耦合到输入/输出焊盘。 N屏蔽也耦合到输入/输出板。下拉驱动器在节点A处的接地和N屏蔽之间耦合。交叉控制电路被配置为检测节点A，节点C和输入/输出板上的电压。交叉控制电路被配置为基于检测到的电压将控制信号输出到P屏蔽和N屏蔽。

3. 发明申请

US20110194218A1 ESD Clamp for High Voltage Operation 有权
标题翻译： ESD钳位用于高电压工作
公开(公告)号：US20110194218A1
公开(公告)日：2011-08-11
申请号：US12701996
申请日：2010-02-08
申请人： Kuo-Ji Chen , Guang-Cheng Wang
发明人： Kuo-Ji Chen , Guang-Cheng Wang
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An electrostatic discharge (ESD) clamp includes a first power source configured to provide a first power supply voltage, a power supply node coupled to the first power source and receiving the power supply voltage; and a first NMOS transistor and a second NMOS transistor coupled in series and between the power supply node and a VSS node. The first NMOS transistor and the second NMOS transistor are low nominal VDD devices with maximum endurable voltages lower than the power supply voltage. The ESD claim further includes an ESD detection circuit including a capacitor coupled between the power supply node and a gate of the second NMOS transistor, and a resistor coupled between the gate of the second NMOS transistor and the VSS node.
摘要翻译：静电放电（ESD）钳位包括被配置为提供第一电源电压的第一电源，耦合到第一电源并接收电源电压的电源节点; 以及串联耦合在电源节点和VSS节点之间的第一NMOS晶体管和第二NMOS晶体管。第一NMOS晶体管和第二NMOS晶体管是具有低于电源电压的最大耐用电压的低标称VDD器件。 ESD声明还包括ESD检测电路，其包括耦合在电源节点和第二NMOS晶体管的栅极之间的电容器，以及耦合在第二NMOS晶体管的栅极和VSS节点之间的电阻器。

4. 发明申请

US20120212279A1 Threshold Voltage Detection Apparatus 有权
标题翻译：阈值电压检测装置
公开(公告)号：US20120212279A1
公开(公告)日：2012-08-23
申请号：US13029469
申请日：2011-02-17
申请人： Bo-Ting Chen , Guang-Cheng Wang
发明人： Bo-Ting Chen , Guang-Cheng Wang
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A threshold voltage detection apparatus comprises a voltage level up-shifter and a voltage level down-shifter. The threshold voltage detection apparatus is placed at a circuit fabricated in a low voltage semiconductor process. The threshold voltage detection apparatus receives an input signal having a wide range and generates output signals comprising the logic of the input signal, but having a voltage range suitable for the low voltage circuit. The threshold voltage detection apparatus ensures that the low voltage circuit operates in a range to which the low voltage semiconductor process is specified.
摘要翻译：阈值电压检测装置包括电压升高移位器和电压电平降档器。阈值电压检测装置放置在以低电压半导体工艺制造的电路上。阈值电压检测装置接收宽范围的输入信号，并产生包括输入信号的逻辑但具有适于低电压电路的电压范围的输出信号。阈值电压检测装置确保低电压电路在指定低电压半导体处理的范围内工作。

5. 发明授权

US07884643B2 Low leakage voltage level shifting circuit 有权
标题翻译：低泄漏电压电平移位电路
公开(公告)号：US07884643B2
公开(公告)日：2011-02-08
申请号：US12494082
申请日：2009-06-29
申请人： Guang-Cheng Wang , Ker-Min Chen , Kuo-Ji Chen
发明人： Guang-Cheng Wang , Ker-Min Chen , Kuo-Ji Chen
IPC分类号： H03K19/094
CPC分类号： H03K3/35613 , H03K3/012
摘要： A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a switching device coupled between a drain of one of the pair of PMOS transistors and a drain of the NMOS transistor, wherein the pair of PMOS transistors are high voltage transistors and the switching device is off when the VCCL is below a predetermined voltage level, and the switching device is on when the VCCL is above the predetermined voltage level.
摘要翻译：公开了一种具有内部低压电源（VCCL）和外部高压电源（VCCH）的集成电路系统的电压电平移动电路，电压电平移位电路包括一对连接到VCCH的交叉耦合PMOS晶体管，源极连接到地（VSS）的NMOS晶体管和连接到在VCCL和VSS之间摆动的第一信号的栅极，以及耦合在一对PMOS晶体管之一的漏极和 NMOS晶体管，其中一对PMOS晶体管是高压晶体管，并且当VCCL低于预定电压电平时，开关器件关断，并且当VCCL高于预定电压电平时，开关器件导通。

6. 发明授权

US08059376B2 ESD clamp for high voltage operation 有权
标题翻译： ESD钳位用于高电压工作
公开(公告)号：US08059376B2
公开(公告)日：2011-11-15
申请号：US12701996
申请日：2010-02-08
申请人： Kuo-Ji Chen , Guang-Cheng Wang
发明人： Kuo-Ji Chen , Guang-Cheng Wang
IPC分类号： H02H9/00 , H01C7/12 , H02H1/00 , H02H1/04 , H02H3/22
CPC分类号： H02H9/046
摘要： An electrostatic discharge (ESD) clamp includes a first power source configured to provide a first power supply voltage, a power supply node coupled to the first power source and receiving the power supply voltage; and a first NMOS transistor and a second NMOS transistor coupled in series and between the power supply node and a VSS node. The first NMOS transistor and the second NMOS transistor are low nominal VDD devices with maximum endurable voltages lower than the power supply voltage. The ESD claim further includes an ESD detection circuit including a capacitor coupled between the power supply node and a gate of the second NMOS transistor, and a resistor coupled between the gate of the second NMOS transistor and the VSS node.
摘要翻译：静电放电（ESD）钳位包括被配置为提供第一电源电压的第一电源，耦合到第一电源并接收电源电压的电源节点; 以及串联耦合在电源节点和VSS节点之间的第一NMOS晶体管和第二NMOS晶体管。第一NMOS晶体管和第二NMOS晶体管是具有低于电源电压的最大耐用电压的低标称VDD器件。 ESD声明还包括ESD检测电路，其包括耦合在电源节点和第二NMOS晶体管的栅极之间的电容器，以及耦合在第二NMOS晶体管的栅极和VSS节点之间的电阻器。

7. 发明申请

US20110089916A1 LDO REGULATORS FOR INTEGRATED APPLICATIONS 有权
标题翻译：集成应用的LDO调节器
公开(公告)号：US20110089916A1
公开(公告)日：2011-04-21
申请号：US12857092
申请日：2010-08-16
申请人： Eric Soenen , Alan Roth , Justin Shi , Ying-Chih Hsu , Guang-Cheng Wang , Wen-Shen Chou
发明人： Eric Soenen , Alan Roth , Justin Shi , Ying-Chih Hsu , Guang-Cheng Wang , Wen-Shen Chou
IPC分类号： G05F1/10
CPC分类号： G05F1/575 , H02M3/07 , H02M2001/0045
摘要： Embodiments of the invention are related to LDO regulators. In an embodiment, an amplifier drives the gate of a master source follower and of at least one slave source follower to form an LDO regulator. In an alternative embodiment, a charge pump drives the master source follower to form the regulator. Additional slave source followers may be used in conjunction with the charge pump and the master source follower to improve the regulator performance. Other embodiments are also disclosed.
摘要翻译：本发明的实施例涉及LDO调节器。在一个实施例中，放大器驱动主源跟随器的栅极和至少一个从源极跟随器的栅极以形成LDO调节器。在替代实施例中，电荷泵驱动主源极跟随器以形成调节器。附加的从源跟随器可以与电荷泵和主源极跟随器一起使用，以改善调节器的性能。还公开了其他实施例。

8. 发明授权

US07611589B2 Methods of spin-on wafer cleaning 有权
标题翻译：旋转晶圆清洗方法
公开(公告)号：US07611589B2
公开(公告)日：2009-11-03
申请号：US11072114
申请日：2005-03-04
申请人： Jun Wu , Dong-Xuan Lu , Shih-Chi Lin , Wen-Long Lee , Yi-An Jian , Guang-Cheng Wang , Shiu-Ko JangJian , Chyi-Tsong Ni , Szu-An Wu , Ying-Lang Wang
发明人： Jun Wu , Dong-Xuan Lu , Shih-Chi Lin , Wen-Long Lee , Yi-An Jian , Guang-Cheng Wang , Shiu-Ko JangJian , Chyi-Tsong Ni , Szu-An Wu , Ying-Lang Wang
IPC分类号： B08B3/02 , B08B1/04
CPC分类号： B08B1/04 , B08B3/02 , H01L21/67051
摘要： A method for spin-on wafer cleaning. The method comprises controlling spin speed and vertical water jet pressure. The vertical jet pressure and the spin speed are substantially maintained in inverse proportion. Wafer spin speed is between 50 to 1200 rpm. Vertical wafer jet pressure is between 0.05 to 100 KPa.
摘要翻译：旋转晶片清洗的方法。该方法包括控制旋转速度和垂直喷水压力。垂直喷射压力和旋转速度基本保持成反比例。晶圆转速在50至1200rpm之间。垂直晶片喷射压力为0.05至100KPa。

9. 发明授权

US08310283B2 Over-drive circuit having stacked transistors 有权
标题翻译：具有堆叠晶体管的过驱动电路
公开(公告)号：US08310283B2
公开(公告)日：2012-11-13
申请号：US12905294
申请日：2010-10-15
申请人： Chia-Hui Chen , Guang-Cheng Wang
发明人： Chia-Hui Chen , Guang-Cheng Wang
IPC分类号： H03K17/08 , H03K19/094 , H03K19/0185
CPC分类号： H03K17/102 , H03K17/08122 , H03K2217/0081
摘要： In a first pair of stacked PMOS devices comprising a first PMOS device and a second PMOS device, a first pumping circuit is coupled between a gate of the first PMOS device and a P pre-driver signal. In a second pair of stacked NMOS devices comprising a first NMOS device and a second NMOS device, a second pumping circuit is coupled between a gate of the first NMOS device and an N pre-driver signal. The pumping circuits recognizing the transition from the pre-driver signals provide a voltage to the gate of the first PMOS device and of the first NMOS device so that the first PMOS and NMOS devices are turned on better. As a result, their voltage Vds peaks are suppressed to a safe level; the devices avoid hot-carrier degradations; and their lifetimes are prolonged.
摘要翻译：在包括第一PMOS器件和第二PMOS器件的第一对堆叠PMOS器件中，第一泵浦电路耦合在第一PMOS器件的栅极和P预驱动器信号之间。在包括第一NMOS器件和第二NMOS器件的第二对堆叠NMOS器件中，第二泵浦电路耦合在第一NMOS器件的栅极和N个预驱动器信号之间。识别来自预驱动器信号的转换的泵浦电路向第一PMOS器件和第一NMOS器件的栅极提供电压，使得第一PMOS和NMOS器件被更好地导通。结果，它们的电压Vds峰值被抑制到安全水平; 器件避免热载体劣化; 他们的寿命延长了。

10. 发明授权

US07940108B1 Voltage level shifter 有权
标题翻译：电压电平转换器
公开(公告)号：US07940108B1
公开(公告)日：2011-05-10
申请号：US12692884
申请日：2010-01-25
申请人： Guang-Cheng Wang , Ta-Pen Guo
发明人： Guang-Cheng Wang , Ta-Pen Guo
IPC分类号： H03L5/00
CPC分类号： H03K19/018528
摘要： A circuit, includes first, second, and third inverters. The first inverter has a first input coupled to a first port and a first output coupled to a second port. The second inverter has a second input coupled to the second port and a second output coupled to the first port. The third inverter has a third input coupled to the first port through a first capacitor and to a third port. The third inverter has an output coupled to the second port through a second capacitor. The circuit receives a signal having a voltage between a first voltage potential and a second voltage potential and in response outputs a signal having a voltage between the second voltage potential and a third voltage potential. The third voltage potential is higher than the first and second voltage potentials with respect to ground.
摘要翻译：电路包括第一，第二和第三逆变器。第一反相器具有耦合到第一端口的第一输入端和耦合到第二端口的第一输出端。第二反相器具有耦合到第二端口的第二输入端和耦合到第一端口的第二输出端。第三反相器具有通过第一电容器耦合到第一端口的第三输入端和第三端口。第三反相器具有通过第二电容器耦合到第二端口的输出。电路接收具有第一电压电位和第二电压电位之间的电压的信号，并且响应于输出具有在第二电压电位和第三电压电位之间的电压的信号。第三电压电位高于相对于地的第一和第二电压电位。

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