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1. 发明授权

US09484462B2 Fin structure of fin field effect transistor 有权
标题翻译：翅片场效应晶体管的鳍结构
公开(公告)号：US09484462B2
公开(公告)日：2016-11-01
申请号：US12766233
申请日：2010-04-23
申请人： Feng Yuan , Hung-Ming Chen , Tsung-Lin Lee , Chang-Yun Chang , Clement Hsingjen Wann
发明人： Feng Yuan , Hung-Ming Chen , Tsung-Lin Lee , Chang-Yun Chang , Clement Hsingjen Wann
IPC分类号： H01L29/06 , H01L29/78 , H01L29/66
CPC分类号： H01L29/66795 , H01L21/308 , H01L29/7851 , H01L29/7853
摘要： An exemplary structure for the fin field effect transistor comprises a substrate comprising a major surface; a plurality of fin structures protruding from the major surface of the substrate, wherein each fin structure comprises an upper portion and a lower portion separated at a transition location at where the sidewall of the fin structure is at an angle of 85 degrees to the major surface of the substrate, wherein the upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate and a top surface having a first width, wherein the lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width; and a plurality of isolation structures between the fin structures, wherein each isolation structure extends from the major surface of the substrate to a point above the transition location.
摘要翻译：鳍状场效应晶体管的示例性结构包括：包括主表面的衬底; 多个翅片结构，从所述基底的主表面突出，其中每个翅片结构包括在翅片结构的侧壁与主表面成85度角的过渡位置处分离的上部和下部，其中所述上部具有基本上垂直于所述基底的主表面的侧壁和具有第一宽度的顶表面，其中所述下部具有在所述上部的相对侧上的锥形侧壁和具有第二宽度的基部宽度大于第一宽度; 以及在翅片结构之间的多个隔离结构，其中每个隔离结构从基板的主表面延伸到过渡位置上方的点。

2. 发明授权

US09953885B2 STI shape near fin bottom of Si fin in bulk FinFET 有权
公开(公告)号：US09953885B2
公开(公告)日：2018-04-24
申请号：US12843693
申请日：2010-07-26
申请人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
发明人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
IPC分类号： H01L21/76 , H01L21/84 , H01L21/762 , H01L21/8234 , H01L29/66
CPC分类号： H01L21/845 , H01L21/76224 , H01L21/823431 , H01L29/66795
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.

3. 发明申请

US20110097889A1 STI Shape Near Fin Bottom of Si Fin in Bulk FinFET 有权
标题翻译：在散装FinFET中的Si Fin附近的STI形状的STI形状
公开(公告)号：US20110097889A1
公开(公告)日：2011-04-28
申请号：US12843693
申请日：2010-07-26
申请人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
发明人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
IPC分类号： H01L21/28
CPC分类号： H01L21/845 , H01L21/76224 , H01L21/823431 , H01L29/66795
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.
摘要翻译：形成集成电路结构的方法包括提供包括顶表面的半导体衬底; 在所述半导体衬底中形成第一绝缘区域和第二绝缘区域; 并使第一绝缘区域和第二绝缘区域凹陷。第一绝缘区域和第二绝缘区域的剩余部分的顶表面是平坦表面或表面。第一绝缘区域和第二绝缘区域的相邻去除部分之间的半导体衬底的一部分形成翅片。

4. 发明申请

US20110084340A1 Voids in STI Regions for Forming Bulk FinFETs 有权
标题翻译：用于形成大量FinFET的STI区域中的空隙
公开(公告)号：US20110084340A1
公开(公告)日：2011-04-14
申请号：US12612442
申请日：2009-11-04
申请人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
发明人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L27/0203 , H01L21/76224 , H01L21/764 , H01L21/823431 , H01L21/823481 , H01L21/845
摘要： An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.
摘要翻译：集成电路结构包括：基板; 两个绝缘区域在衬底上，两个绝缘区域中的一个在其中包括空隙; 以及在所述两个绝缘区域之间并邻接所述两个绝缘区域的第一半导体条带。第一半导体条包括在两个绝缘区域的顶表面上形成翅片的顶部部分。

5. 发明授权

US08592918B2 Forming inter-device STI regions and intra-device STI regions using different dielectric materials 有权
标题翻译：使用不同的介电材料形成器件间STI区和器件内部区域
公开(公告)号：US08592918B2
公开(公告)日：2013-11-26
申请号：US12843658
申请日：2010-07-26
申请人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
发明人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
IPC分类号： H01L21/02
CPC分类号： H01L21/76224 , H01L21/76229 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211
摘要： An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.
摘要翻译：集成电路结构包括具有第一器件区域中的第一部分和第二器件区域中的第二部分的衬底; 以及在第一器件区域和衬底上的两个绝缘区域。两个绝缘区域包括具有第一k值的第一电介质材料。半导体条在两个绝缘区之间并相邻，半导体条的顶部在两个绝缘区的顶表面上形成半导体鳍。另外的绝缘区域位于第二器件区域和衬底之上。附加绝缘区域包括具有大于第一k值的第二k值的第二电介质材料。

6. 发明授权

US08519481B2 Voids in STI regions for forming bulk FinFETs 有权
标题翻译：在STI区域中形成大块FinFET的空隙
公开(公告)号：US08519481B2
公开(公告)日：2013-08-27
申请号：US12612442
申请日：2009-11-04
申请人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
发明人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
IPC分类号： H01L27/088
CPC分类号： H01L27/0203 , H01L21/76224 , H01L21/764 , H01L21/823431 , H01L21/823481 , H01L21/845
摘要： An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.
摘要翻译：集成电路结构包括：基板; 两个绝缘区域在衬底上，两个绝缘区域中的一个在其中包括空隙; 以及在所述两个绝缘区域之间并相邻的第一半导体条带。第一半导体条包括在两个绝缘区域的顶表面上形成翅片的顶部部分。

7. 发明申请

US20110095372A1 Forming Inter-Device STI Regions and Intra-Device STI Regions Using Different Dielectric Materials 有权
标题翻译：使用不同介质材料形成器件间STI区域和器件内STI区域
公开(公告)号：US20110095372A1
公开(公告)日：2011-04-28
申请号：US12843658
申请日：2010-07-26
申请人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
发明人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
IPC分类号： H01L27/088
CPC分类号： H01L21/76224 , H01L21/76229 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211
摘要： An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.
摘要翻译：集成电路结构包括具有第一器件区域中的第一部分和第二器件区域中的第二部分的衬底; 以及在第一器件区域和衬底上的两个绝缘区域。两个绝缘区域包括具有第一k值的第一电介质材料。半导体条在两个绝缘区之间并相邻，半导体条的顶部在两个绝缘区的顶表面上形成半导体鳍。另外的绝缘区域位于第二器件区域和衬底之上。附加绝缘区域包括具有大于第一k值的第二k值的第二电介质材料。

8. 发明授权

US08623718B2 Tilt implantation for forming FinFETs 有权
标题翻译：用于形成FinFET的倾斜植入
公开(公告)号：US08623718B2
公开(公告)日：2014-01-07
申请号：US13247570
申请日：2011-09-28
申请人： Feng Yuan , Tsung-Lin Lee , Shao-Ming Yu , Clement Hsingjen Wann
发明人： Feng Yuan , Tsung-Lin Lee , Shao-Ming Yu , Clement Hsingjen Wann
IPC分类号： H01L21/00
CPC分类号： H01L29/66803
摘要： In a method for forming FinFETs, a photo resist is formed to cover a first semiconductor fin in a wafer, wherein a second semiconductor fin adjacent to the first semiconductor fin is not covered by the photo resist. An edge of the photo resist between and parallel to the first and the second semiconductor fins is closer to the first semiconductor fin than to the second semiconductor fin. A tilt implantation is performed to form a lightly-doped source/drain region in the second semiconductor fin, wherein the first tilt implantation is tilted from the second semiconductor fin toward the first semiconductor fin.
摘要翻译：在形成FinFET的方法中，形成光致抗蚀剂以覆盖晶片中的第一半导体鳍片，其中与第一半导体鳍片相邻的第二半导体鳍片不被光致抗蚀剂覆盖。第一半导体鳍片和第二半导体鳍片之间的平行于第一和第二半导体鳍片的光刻胶的边缘比第二半导体鳍片更靠近第一半导体鳍片。进行倾斜注入以在第二半导体鳍片中形成轻掺杂的源极/漏极区域，其中第一倾斜注入从第二半导体鳍片向第一半导体鳍片倾斜。

9. 发明申请

US20130078772A1 Tilt Implantation for Forming FinFETs 有权
标题翻译：用于形成FinFET的倾斜植入
公开(公告)号：US20130078772A1
公开(公告)日：2013-03-28
申请号：US13247570
申请日：2011-09-28
申请人： Feng Yuan , Tsung-Lin Lee , Shao-Ming Yu , Clement Hsingjen Wann
发明人： Feng Yuan , Tsung-Lin Lee , Shao-Ming Yu , Clement Hsingjen Wann
IPC分类号： H01L21/336
CPC分类号： H01L29/66803
摘要： In a method for forming FinFETs, a photo resist is formed to cover a first semiconductor fin in a wafer, wherein a second semiconductor fin adjacent to the first semiconductor fin is not covered by the photo resist. An edge of the photo resist between and parallel to the first and the second semiconductor fins is closer to the first semiconductor fin than to the second semiconductor fin. A tilt implantation is performed to form a lightly-doped source/drain region in the second semiconductor fin, wherein the first tilt implantation is tilted from the second semiconductor fin toward the first semiconductor fin.
摘要翻译：在形成FinFET的方法中，形成光致抗蚀剂以覆盖晶片中的第一半导体鳍片，其中与第一半导体鳍片相邻的第二半导体鳍片不被光致抗蚀剂覆盖。第一半导体鳍片和第二半导体鳍片之间的平行于第一和第二半导体鳍片的光刻胶的边缘比第二半导体鳍片更靠近第一半导体鳍片。进行倾斜注入以在第二半导体鳍片中形成轻掺杂的源极/漏极区域，其中第一倾斜注入从第二半导体鳍片向第一半导体鳍片倾斜。

10. 发明申请

US20130075818A1 3D Semiconductor Device and Method of Manufacturing Same 审中-公开
标题翻译： 3D半导体器件及其制造方法相同
公开(公告)号：US20130075818A1
公开(公告)日：2013-03-28
申请号：US13243723
申请日：2011-09-23
申请人： Tsung-Lin Lee , Feng Yuan , Chih Chieh Yeh , Clement Hsingjen Wann
发明人： Tsung-Lin Lee , Feng Yuan , Chih Chieh Yeh , Clement Hsingjen Wann
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L21/28088 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0886 , H01L27/0924 , H01L27/1211 , H01L29/66545 , H01L29/7845 , H01L29/785
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate and a 3D structure disposed over the substrate. The semiconductor device further includes a dielectric layer disposed over the 3D structure, a WFMG layer disposed over the dielectric layer, and a gate structure disposed over the WFMG layer. The gate structure traverses the 3D structure and separates a source region and a drain region of the 3D structure. The source and drain region define a channel region therebetween. The gate structure induces a stress in the channel region.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。示例性的半导体器件包括衬底和设置在衬底上的3D结构。半导体器件还包括设置在3D结构上的电介质层，设置在电介质层上的WFMG层，以及设置在WFMG层上的栅极结构。栅极结构横穿3D结构并分离3D结构的源极区域和漏极区域。源极和漏极区域在其间限定沟道区域。栅极结构在沟道区域中引起应力。

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