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    • 2. 发明授权
    • Trench isolation regions having recess-inhibiting layers therein that protect against overetching
    • 沟槽隔离区域在其中具有防止过蚀刻的凹陷抑制层
    • US06717231B2
    • 2004-04-06
    • US10224017
    • 2002-08-20
    • Sung-eui KimKeum-joo LeeIn-seak HwangYoung-sun KohDong-ho AhnMoon-han ParkTai-su Park
    • Sung-eui KimKeum-joo LeeIn-seak HwangYoung-sun KohDong-ho AhnMoon-han ParkTai-su Park
    • H01L2176
    • H01L21/76224
    • Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.
    • 形成沟槽隔离区域的方法包括以下步骤:在其中形成具有沟槽的半导体衬底和其上邻近沟槽延伸的掩模层。 掩模层可以包括氮化硅。 然后在沟槽的侧壁和掩模层的侧壁上形成凹陷抑制层。 接下来,在凹陷抑制层上形成应力消除层。 该应力消除层与沟槽的侧壁相对并且与掩模层的侧壁相对延伸并且可以包括氮化硅。 然后用沟槽隔离层填充沟槽。 然后执行一系列平面化或蚀刻步骤以去除掩模层,并且还使沟槽隔离层的上表面与衬底的表面对准。 使用第一蚀刻剂(例如磷酸)去除掩模层的至少一部分,其以比第一凹陷抑制层更快的速率选择性地蚀刻掩模层和应力消除层。 凹陷抑制层直接形成在掩模层的侧壁上,以限制应力消除层的外表面暴露于第一蚀刻剂的程度。 以这种方式,可以减少应力消除层的凹陷和随后可能由于凹陷而形成的空隙。 还可以提供多个薄的应力消除层,并且这些多层提供与单个更厚的应力消除层相当的应力消除程度。
    • 3. 发明授权
    • Methods of forming trench isolation regions having recess-inhibiting layers therein that protect against overetching
    • 形成其中具有防止过蚀刻的凹陷抑制层的沟槽隔离区的方法
    • US06461937B1
    • 2002-10-08
    • US09479442
    • 2000-01-07
    • Sung-eui KimKeum-joo LeeIn-seak HwangYoung-sun KohDong-ho AhnMoon-han ParkTai-su Park
    • Sung-eui KimKeum-joo LeeIn-seak HwangYoung-sun KohDong-ho AhnMoon-han ParkTai-su Park
    • H01L2176
    • H01L21/76224
    • Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.
    • 形成沟槽隔离区域的方法包括以下步骤:在其中形成具有沟槽的半导体衬底和其上邻近沟槽延伸的掩模层。 掩模层可以包括氮化硅。 然后在沟槽的侧壁和掩模层的侧壁上形成凹陷抑制层。 接下来,在凹陷抑制层上形成应力消除层。 该应力消除层与沟槽的侧壁相对并且与掩模层的侧壁相对延伸并且可以包括氮化硅。 然后用沟槽隔离层填充沟槽。 然后执行一系列平面化或蚀刻步骤以去除掩模层,并且还使沟槽隔离层的上表面与衬底的表面对准。 使用第一蚀刻剂(例如磷酸)去除掩模层的至少一部分,其以比第一凹陷抑制层更快的速率选择性地蚀刻掩模层和应力消除层。 凹陷抑制层直接形成在掩模层的侧壁上,以限制应力消除层的外表面暴露于第一蚀刻剂的程度。 以这种方式,可以减少应力消除层的凹陷和随后可能由于凹陷而形成的空隙。 还可以提供多个薄的应力消除层,并且这些多层提供与单个更厚的应力消除层相当的应力消除程度。
    • 4. 发明授权
    • Isolation method of semiconductor device using second pad oxide layer
formed through chemical vapor deposition (CVD)
    • 使用通过化学气相沉积(CVD)形成的第二衬垫氧化物层的半导体器件的隔离方法
    • US6093622A
    • 2000-07-25
    • US148060
    • 1998-09-04
    • Dong-ho AhnSung-eui KimYu-gyun Shin
    • Dong-ho AhnSung-eui KimYu-gyun Shin
    • H01L21/285H01L21/316H01L21/76H01L21/762
    • H01L21/76202
    • An isolation method in the fabrication process of a semiconductor device is provided. The method forms an oxide layer as a buffer layer for reducing stress through chemical vapor deposition (CVD). By the method, a first pad oxide layer and a silicon nitride layer are formed on a semiconductor substrate, and then an silicon nitride layer pattern is formed by patterning, and undercuts are formed in the first pad oxide layer pattern. Subsequently, a second pad oxide layer is formed on the entire surface of the semiconductor substrate through CVD, and then spacers are formed on the sidewalls of both the patterned first pad oxide layer and silicon nitride layer and a field oxide layer is formed through thermal oxidation. Alternatively, a silicon layer is deposited without the spacers to form the field oxide layer. The second pad oxide layer is a buffer layer for buffering stress during formation of the field oxide layer.
    • 提供了半导体器件的制造工艺中的隔离方法。 该方法形成通过化学气相沉积(CVD)来减少应力的缓冲层的氧化物层。 通过该方法,在半导体衬底上形成第一衬垫氧化物层和氮化硅层,然后通过图案形成氮化硅层图案,并且在第一衬垫氧化物层图案中形成底切。 随后,通过CVD在半导体衬底的整个表面上形成第二焊盘氧化物层,然后在图案化的第一焊盘氧化物层和氮化硅层的侧壁上形成间隔物,并且通过热氧化形成场氧化物层 。 或者,沉积硅层而没有间隔物以形成场氧化物层。 第二衬垫氧化物层是用于在形成场氧化物层期间缓冲应力的缓冲层。
    • 7. 发明授权
    • Methods of fabricating combined field oxide/trench isolation regions
    • 组合场氧化物/沟槽隔离区域的方法
    • US5677232A
    • 1997-10-14
    • US754889
    • 1996-11-22
    • Sung-eui KimSoo-jin Hong
    • Sung-eui KimSoo-jin Hong
    • H01L21/316H01L21/76H01L21/762
    • H01L21/76202H01L21/76229H01L21/76235
    • An isolation region is formed on a substrate by forming spaced apart mesas on the substrate. A first insulation region is then formed on the substrate and second insulation regions are formed on the mesas, the first insulation region being disposed between and spaced apart from a respective one of the mesas, a respective one of the second insulation regions capping a respective one of the mesas. Preferably, the first and second insulation regions are formed by forming sidewall spacers adjacent sidewall portions of the mesas and oxidizing portions of the mesas opposite the substrate and a portion of the substrate disposed between the sidewall spacers. Spaced apart trenches are formed in the substrate on opposite sides of the first insulation region, a respective one of the trenches being disposed between the first insulation region and a respective one of the mesas, preferably by removing the sidewall spacers and underlying portions of the substrate. An insulating layer is formed on the substrate, filling the trenches and covering the first insulation region, and the substrate is planarized to remove portions of the insulating layer and the second insulation regions and thereby expose underlying portions of the mesas and leave a third insulation region spanning the trenches.
    • 通过在衬底上形成间隔开的台面,在衬底上形成隔离区。 然后在基板上形成第一绝缘区域,并且在台面上形成第二绝缘区域,第一绝缘区域设置在相应的一个台面之间并与相应的一个台面间隔开,第一绝缘区域中的相应一个覆盖相应的一个 的台面。 优选地,第一和第二绝缘区域通过形成邻近台面的侧壁部分的侧壁间隔和与衬底相对的台面的氧化部分和设置在侧壁间隔件之间的衬底的一部分而形成。 隔开的沟槽在第一绝缘区域的相对侧上的衬底中形成,相应的沟槽设置在第一绝缘区域和相应的台面之间,优选地通过去除侧壁间隔件和衬底的下面部分 。 在衬底上形成绝缘层,填充沟槽并覆盖第一绝缘区域,并且将衬底平坦化以去除绝缘层和第二绝缘区域的部分,从而暴露台面的下面部分并留下第三绝缘区域 跨越壕沟