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1. 发明授权

US09123589B2 Display substrate including an auxiliary electrode 有权
标题翻译：显示基板，包括辅助电极
公开(公告)号：US09123589B2
公开(公告)日：2015-09-01
申请号：US13422686
申请日：2012-03-16
申请人： Min-Wook Park , Jong-In Kim , Jun-Ho Song , Bum-Ki Baek , Young-Soo Yoon
发明人： Min-Wook Park , Jong-In Kim , Jun-Ho Song , Bum-Ki Baek , Young-Soo Yoon
IPC分类号： G02F1/1333 , H01L33/08 , H01L27/12 , G02F1/1362
CPC分类号： H01L27/124 , G02F1/1362 , H01L27/1255
摘要： A display substrate includes a data line, a main gate line, and a first sub-pixel electrode formed on a base substrate. The display substrate further includes a first switching element connected to the data line. The display substrate further includes a second switching element connected to the data line, the main gate line, and a second sub-pixel electrode spaced apart from the first sub-pixel electrode. The display substrate further includes a third switching element connected to the data line and a secondary gate line adjacent to the main gate line. The display substrate further includes a shielding line spaced apart from the first and second sub-pixel electrodes, the shielding line overlapping the data line and receiving a reference voltage. The display substrate further includes an auxiliary electrode extending from the shielding line and overlapping an end electrode connected to the third switching element.
摘要翻译：显示基板包括形成在基底基板上的数据线，主栅线和第一子像素电极。显示基板还包括连接到数据线的第一开关元件。显示基板还包括连接到数据线，主栅极线和与第一子像素电极间隔开的第二子像素电极的第二开关元件。显示基板还包括连接到数据线的第三开关元件和与主栅极线相邻的次级栅极线。显示基板还包括与第一和第二子像素电极间隔开的屏蔽线，屏蔽线与数据线重叠并接收参考电压。显示基板还包括从屏蔽线延伸并与连接到第三开关元件的端电极重叠的辅助电极。

2. 发明授权

US08952878B2 Display device 有权
标题翻译：显示设备
公开(公告)号：US08952878B2
公开(公告)日：2015-02-10
申请号：US13517872
申请日：2012-06-14
申请人： Jae Hwa Park , Yeo Geon Yoon , Jang-Il Kim , Kyung Ho Kim , Jong-In Kim , Min-Wook Park , Bum Ki Baek , Joon-Chul Goh , Young-Soo Yoon , Hak Bum Choi , Hyo-Seop Kim
发明人： Jae Hwa Park , Yeo Geon Yoon , Jang-Il Kim , Kyung Ho Kim , Jong-In Kim , Min-Wook Park , Bum Ki Baek , Joon-Chul Goh , Young-Soo Yoon , Hak Bum Choi , Hyo-Seop Kim
IPC分类号： G09G3/36 , G02F1/1345 , G02F1/1362
CPC分类号： G02F1/136286 , G02F1/13452 , G02F1/13458 , G02F1/136213 , G02F1/13624 , G02F1/1368 , G09G3/3648 , G09G3/3655 , G09G2300/0426 , G09G2300/0876 , G09G2320/0233 , H01L27/124
摘要： A display device includes gate lines, data lines, first wires and second wires extending in the directions of the gate lines and data lines, and pixels having a first subpixel and a second subpixel each. The first subpixel has a first subpixel electrode and a first switching element, and the second subpixel has a second subpixel electrode and second and third switching elements. The control terminals of the three switching elements are connected to the same gate line, and the input terminals of the first and second switching elements are connected to the same data line. The first and second switching elements have output terminals connected to the first and second subpixel electrodes, respectively. The second switching element's output terminal connects to the third switching element, which has an output terminal connected to a second wire. The first wires and the second wires are connected in a pixel.
摘要翻译：显示装置包括栅极线，数据线，第一布线和沿着栅极线和数据线的方向延伸的第二布线，以及具有第一子像素和第二子像素的像素。第一子像素具有第一子像素电极和第一开关元件，第二子像素具有第二子像素电极和第二以及第三开关元件。三个开关元件的控制端子连接到相同的栅极线，并且第一和第二开关元件的输入端子连接到相同的数据线。第一和第二开关元件分别具有连接到第一和第二子像素电极的输出端子。第二开关元件的输出端子连接到具有连接到第二导线的输出端子的第三开关元件。第一线和第二线连接在一个像素中。

3. 发明授权

US07320906B2 Thin film transistor array panel and manufacturing method thereof 有权
公开(公告)号：US07320906B2
公开(公告)日：2008-01-22
申请号：US10922343
申请日：2004-08-19
申请人： Min-Wook Park , Bum-Ki Baek , Jeong-Young Lee , Kwon-Young Choi , Sang-Ki Kwak , Sang-Jin Jeon
发明人： Min-Wook Park , Bum-Ki Baek , Jeong-Young Lee , Kwon-Young Choi , Sang-Ki Kwak , Sang-Jin Jeon
IPC分类号： H01L21/84
CPC分类号： H01L29/41733 , H01L27/124
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

4. 发明授权

US07566906B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07566906B2
公开(公告)日：2009-07-28
申请号：US11958230
申请日：2007-12-17
申请人： Min-Wook Park , Bum-Ki Baek , Jeong-Young Lee , Kwon-Young Choi , Sang-Ki Kwak , San-Jin Jeon
发明人： Min-Wook Park , Bum-Ki Baek , Jeong-Young Lee , Kwon-Young Choi , Sang-Ki Kwak , San-Jin Jeon
IPC分类号： H01L29/04
CPC分类号： H01L29/41733 , H01L27/124
摘要： A thin film transistor array panel is provided, which includes a substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a plurality of ohmic contacts formed on the semiconductor layer; source and drain electrodes formed on the ohmic contacts; a passivation layer formed on the source and the drain electrodes and having a first contact hole exposing a portion of the drain electrode and an opening exposing a first portion of the semiconductor layer and having edges that coincide with edges of the source and the drain electrodes; and a pixel electrode formed on the passivation layer and contacting the drain electrode through the first contact hole.
摘要翻译：提供薄膜晶体管阵列面板，其包括基板; 形成在所述基板上并包括栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在所述栅极绝缘层上的半导体层; 形成在所述半导体层上的多个欧姆接触; 源极和漏极形成在欧姆接触上; 形成在源电极和漏电极上的钝化层，具有露出漏电极的一部分的第一接触孔和露出半导体层的第一部分并且具有与源电极和漏电极的边缘重合的边缘的开口; 以及形成在钝化层上并通过第一接触孔接触漏电极的像素电极。

5. 发明授权

US07459323B2 Method of manufacturing a thin film transistor array panel 有权
标题翻译：制造薄膜晶体管阵列面板的方法
公开(公告)号：US07459323B2
公开(公告)日：2008-12-02
申请号：US11512805
申请日：2006-08-30
申请人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
发明人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
IPC分类号： H01L21/00
CPC分类号： G02F1/1368 , G02F1/1339
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

6. 发明申请

US20060289965A1 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20060289965A1
公开(公告)日：2006-12-28
申请号：US11512805
申请日：2006-08-30
申请人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
发明人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： G02F1/1368 , G02F1/1339
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

7. 发明申请

US20050082535A1 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20050082535A1
公开(公告)日：2005-04-21
申请号：US10926719
申请日：2004-08-26
申请人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
发明人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
IPC分类号： G02F1/136 , G02F1/133 , G02F1/1339 , G02F1/1368 , G03C1/85 , G03C5/00 , G09F9/30 , H01L21/00 , H01L21/336 , H01L29/786
CPC分类号： G02F1/1368 , G02F1/1339
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

8. 发明授权

US07119368B2 Thin film transistor array panel and manufacturing method thereof 有权
公开(公告)号：US07119368B2
公开(公告)日：2006-10-10
申请号：US10926719
申请日：2004-08-26
申请人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
发明人： Min-Wook Park , Sang-Jin Jeon , Jung-Joon Park , Jeong-Young Lee , Bum-Ki Baek , Se-Hwan Yu , Sang-Ki Kwak , Han-Ju Lee , Kwon-Young Choi
IPC分类号： H01L31/0376
CPC分类号： G02F1/1368 , G02F1/1339
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

9. 发明申请

US20050110014A1 Thin film transistor array panel and manufacturing method thereof 有权
公开(公告)号：US20050110014A1
公开(公告)日：2005-05-26
申请号：US10922343
申请日：2004-08-19
申请人： Min-Wook Park , Bum-Ki Baek , Jeong-Young Lee , Kwon-Young Choi , Sang-Ki Kwak , Sang-Jin Jeon
发明人： Min-Wook Park , Bum-Ki Baek , Jeong-Young Lee , Kwon-Young Choi , Sang-Ki Kwak , Sang-Jin Jeon
IPC分类号： G02F1/1339 , G02F1/136 , G02F1/1368 , G09F9/00 , G09F9/30 , H01L21/00 , H01L21/3205 , H01L21/3213 , H01L21/336 , H01L21/77 , H01L21/84 , H01L23/52 , H01L29/417 , H01L29/786 , H01L31/036
CPC分类号： H01L29/41733 , H01L27/124
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

10. 发明授权

US08502949B2 Display panel and display apparatus having the same 有权
标题翻译：显示面板和具有该显示面板的显示装置
公开(公告)号：US08502949B2
公开(公告)日：2013-08-06
申请号：US13084182
申请日：2011-04-11
申请人： Kyoung-Tai Han , Eun-Guk Lee , Young-Goo Song , Hyuk-Jin Kim , Min-Wook Park , Jong-In Kim , Hyo-Seop Kim
发明人： Kyoung-Tai Han , Eun-Guk Lee , Young-Goo Song , Hyuk-Jin Kim , Min-Wook Park , Jong-In Kim , Hyo-Seop Kim
IPC分类号： G02F1/1343 , G02F1/1333 , G02F1/133
CPC分类号： G09G3/3648 , G02F1/13336 , G02F1/133512 , G09G2310/0232
摘要： A display panel includes a first display substrate, a second display substrate, and a liquid crystal layer. The first display substrate includes a first base substrate having a plurality of display cells, a plurality of data lines, a plurality of gate lines, and a plurality of pixel electrodes. The data lines, the gate lines and the pixel electrodes are respectively separated in each of the display cells. The second display substrate includes a second base substrate, a light blocking pattern corresponding to the data lines and the gate lines, a common electrode facing the pixel electrodes, and a common line overlapping with the blocking pattern. The liquid crystal layer is disposed between the first and second display substrate.
摘要翻译：显示面板包括第一显示基板，第二显示基板和液晶层。第一显示基板包括具有多个显示单元，多条数据线，多条栅极线和多个像素电极的第一基板。数据线，栅极线和像素电极分别在每个显示单元中分离。第二显示基板包括第二基底基板，对应于数据线和栅极线的遮光图案，面对像素电极的公共电极以及与阻挡图案重叠的公共线。液晶层设置在第一和第二显示基板之间。

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