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1. 发明授权

US5490119A Semiconductor device including signal generating circuit with level converting function and with reduced area of occupation 失效
标题翻译：半导体器件包括具有电平转换功能的信号发生电路和占用面积减少
公开(公告)号：US5490119A
公开(公告)日：1996-02-06
申请号：US229274
申请日：1994-04-18
申请人： Mikio Sakurai , Kenji Tokami , Kazuhiro Sakemi , Yutaka Ikeda , Yoshinori Inoue , Takeshi Kajimoto
发明人： Mikio Sakurai , Kenji Tokami , Kazuhiro Sakemi , Yutaka Ikeda , Yoshinori Inoue , Takeshi Kajimoto
IPC分类号： G11C11/418 , G11C8/08 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C8/00
CPC分类号： G11C8/12 , G11C8/08
摘要： A semiconductor memory device includes a pull up circuit (811) for pulling up a potential of a first node (812), a pull down circuit (813) for pulling down the potential of the first node, an inverter circuit (814b) having its input connected to a first input node (814a) connected to the first node (812) and its output connected to a first output node (814c) and operating with a boosted potential Vpp, and a p channel MOS transistor (814d) connected between a boosted potential node (50c) and the first input node (814a), with its gate electrode connected to the first output node (814c). The memory device provides a signal having a higher level than the supply potential with smaller area of layout.
摘要翻译：半导体存储器件包括用于提升第一节点（812）的电位的上拉电路（811），用于下拉第一节点的电位的下拉电路（813），具有其的连接到连接到第一节点（812）的第一输入节点（814a）的输入端，并且其输出端连接到第一输出节点（814c）并且用升压电位Vpp操作，以及连接在升压的电压Vpp之间的ap沟道MOS晶体管（814d）电势节点（50c）和第一输入节点（814a），其栅电极连接到第一输出节点（814c）。存储器件提供具有比电源电位更高的电平的信号，具有较小的布局面积。

2. 发明授权

US5519650A Semiconductor device having an improved immunity to a short-circuit at a power supply line 失效
标题翻译：具有对电源线短路的抗干扰性的半导体装置
公开(公告)号：US5519650A
公开(公告)日：1996-05-21
申请号：US301752
申请日：1994-09-07
申请人： Tooru Ichimura , Kazuhiro Sakemi , Shigeru Mori , Mikio Sakurai
发明人： Tooru Ichimura , Kazuhiro Sakemi , Shigeru Mori , Mikio Sakurai
IPC分类号： G11C11/41 , G11C29/50 , H01L21/3205 , H01L21/82 , H01L23/52 , H01L23/525 , G11C5/06
CPC分类号： G11C29/50 , H01L23/5258 , H01L2924/0002
摘要： A semiconductor memory device includes a memory cell array (1) having a plurality of memory cells arranged in rows and columns, a plurality of column select lines (3) extending over the memory cell array and coupled to received column select signals generated by a column decoder (100), a plurality of power supply lines (4) provided in parallel with the column select lines to transfer a power supply voltage from a main power supply line (130), and a plurality of ground lines (5) provided in parallel with the column select lines to transfer a ground voltage from a main ground line. A plurality of fuse elements (6) are provided for each of the column select lines. When a short-circuit is found between a column select line and power supply line or a ground line, a fuse element corresponding to the short-circuited column select line is blown off and the short-circuited column select line is isolated from the column decoder. By repairing the short-circuited column select line with a redundant column select line (60), the memory device operates correctly without an adverse effect of the short-circuit.
摘要翻译：半导体存储器件包括具有以行和列排列的多个存储器单元的存储单元阵列（1），在存储单元阵列上延伸的多个列选择线（3），并与由列产生的接收列选择信号耦合解码器（100），与列选择线并联设置的多个电源线（4），用于传送来自主电源线（130）的电源电压和并联设置的多个接地线（5）列选择线从主地线传输接地电压。为每个列选择线提供多个熔丝元件（6）。当在列选择线和电源线或接地线之间发现短路时，与短路列选择线相对应的熔丝元件被断开，并且短路列选择线与列解码器隔离。通过修复具有冗余列选择线（60）的短路列选择线，存储器件正常工作而没有短路的不利影响。

3. 发明申请

US20050235101A1 Memory controller, semiconductor integrated circuit device, semiconductor device, microcomputer, and electronic device 失效
标题翻译：存储控制器，半导体集成电路器件，半导体器件，微计算机和电子器件
公开(公告)号：US20050235101A1
公开(公告)日：2005-10-20
申请号：US11100228
申请日：2005-04-06
申请人： Mikio Sakurai
发明人： Mikio Sakurai
IPC分类号： G06F12/00 , G06F13/16 , G11C11/406
CPC分类号： G06F13/1636
摘要： A memory controller is connected with a first memory requiring refresh and a second memory not requiring refresh, both of which share part of a bus, comprising: a first memory controller that conducts access control and auto-refresh control for the first memory; a second memory controller that conducts access control for the second memory; and an arbiter that adjusts the timing of outputting a signal generated for the first memory and another signal generated for the second memory to a bus, wherein, with a judgment that the signal from the first memory controller is an auto-refresh request, a refresh request signal for the first memory is outputted even while the second memory is being accessed.
摘要翻译：存储器控制器与需要刷新的第一存储器和不需要刷新的第二存储器连接，二者共享总线的一部分，包括：对第一存储器进行访问控制和自动刷新控制的第一存储器控制器; 执行第二存储器的访问控制的第二存储器控制器; 以及仲裁器，其将对所述第一存储器生成的信号和将所述第二存储器生成的信号的输出的时序输出到总线的定时，其中，通过判断来自所述第一存储器控制器的信号是自动刷新请求，即使在访问第二存储器时也输出第一存储器的请求信号。

4. 发明授权

US5488247A MOS-type semiconductor clamping circuit 失效
标题翻译： MOS型半导体钳位电路
公开(公告)号：US5488247A
公开(公告)日：1996-01-30
申请号：US277817
申请日：1994-07-20
申请人： Mikio Sakurai
发明人： Mikio Sakurai
IPC分类号： H01L27/04 , G05F3/24 , H01L21/822 , H03G11/00 , H01L29/78 , H01H35/00 , H02B1/24
CPC分类号： G05F3/24 , H01L2924/0002 , Y10S257/928 , Y10T307/766
摘要： A MOS-type semiconductor clamping circuit includes a semiconductor substrate receiving a substrate potential, a well isolated electrically from the substrate potential, and MOS-type transistors formed in the well. Those transistors are connected with each other in series, each transistor has its gate connected to its drain, and a stable potential different from the substrate potential is applied to the well.
摘要翻译： MOS型半导体钳位电路包括接收衬底电位的半导体衬底，与衬底电位电隔离的阱，以及形成在阱中的MOS型晶体管。这些晶体管串联连接，每个晶体管的栅极连接到其漏极，并且将不同于衬底电位的稳定电位施加到阱。

5. 发明授权

US5959930A Multi-bank synchronous semiconductor memory device 失效
标题翻译：多组同步半导体存储器件
公开(公告)号：US5959930A
公开(公告)日：1999-09-28
申请号：US30001
申请日：1998-02-25
申请人： Mikio Sakurai
发明人： Mikio Sakurai
IPC分类号： G11C11/401 , G11C7/10 , G11C8/12 , G11C11/407 , G11C8/00
CPC分类号： G11C8/12 , G11C7/1072
摘要： A plurality of memory banks are activated to select a memory cell in response to a bank select signal from a bank select signal generating circuit. When a special mode of operation is designated, a mode setting circuit activates all of bank select signals from the bank select signal generating circuit to simultaneously drive all memory banks to active/inactive state. Thus, a multi-bank, a synchronous semiconductor memory device capable of accessing memory cells at high speed and efficiently selecting memory cells is obtained.
摘要翻译：响应于来自存储体选择信号发生电路的存储体选择信号，多个存储体被激活以选择存储单元。当指定特殊操作模式时，模式设置电路激活来自存储体选择信号发生电路的所有存储体选择信号，以同时驱动所有存储体到主动/不活动状态。因此，可以获得能够高速访问存储单元并有效地选择存储单元的多存储体，同步半导体存储器件。

6. 发明授权

US4337118A Nuclear reactor power monitoring system 失效
标题翻译：核反应堆电力监控系统
公开(公告)号：US4337118A
公开(公告)日：1982-06-29
申请号：US84437
申请日：1979-10-12
申请人： Mikio Sakurai , Yuichiro Yoshimoto , Hiroshi Kodama
发明人： Mikio Sakurai , Yuichiro Yoshimoto , Hiroshi Kodama
IPC分类号： G21C7/26 , G21D3/10 , G21C7/00
CPC分类号： G21D3/10 , Y02E30/40
摘要： A nuclear reactor power monitoring system for monitoring the power level of a reactor and preventing an excessive rise thereof attributable to a transient increase in the core coolant flow rate before the reactor is scrammed. The system include an operating region monitor (ORM) for blocking the increase in the core coolant flow rate or running-back the flow rate when the power level exceeds a predetermined coolant block threshold power level which is a function of the core coolant flow rate.
摘要翻译：一种核反应堆功率监测系统，用于监测反应堆的功率水平并防止由于反应堆被击倒之前核心冷却剂流速的瞬时增加而导致的过度上升。该系统包括操作区域监视器（ORM），用于当功率水平超过作为芯冷却剂流量的函数的预定冷却剂块阈值功率水平时阻止核心冷却剂流量的增加或回流流量。

7. 发明申请

US20100060760A1 IMAGING APPARATUS AND DUST REDUCTION APPARATUS 审中-公开
标题翻译：成像装置和减尘装置
公开(公告)号：US20100060760A1
公开(公告)日：2010-03-11
申请号：US12556631
申请日：2009-09-10
申请人： Mikio Sakurai
发明人： Mikio Sakurai
IPC分类号： H04N5/335 , F28G7/00
CPC分类号： H04N5/2254
摘要： An imaging apparatus includes an imaging device operable to convert light to an electrical signal, a vibrating unit including an optical member arranged on a light-receiving surface side of the imaging device, a vibration applying unit arranged to contact the vibrating unit and vibrates upon application of a voltage, the vibration applying unit vibrating integrally with the vibrating unit to vibrate the vibrating unit, and a member operable to sandwich the vibrating unit and the vibration applying unit. A zero-amplitude reference plane of resonance produced by the integral vibration of the vibrating unit and the vibration applying unit is located on the vibrating unit.
摘要翻译：一种成像装置，包括可将光转换为电信号的成像装置，包括配置在摄像装置的受光面侧的光学部件的振动单元，配置为接触振动单元并在施加时振动的振动施加单元所述振动施加单元与所述振动单元一体地振动以振动所述振动单元，以及可操作地夹持所述振动单元和所述振动施加单元的构件。由振动单元和振动施加单元的整体振动产生的共振零参考平面位于振动单元上。

8. 发明授权

US05999472A Multi-bank synchronous semiconductor memory device with easy control 失效
标题翻译：多组同步半导体存储器件易于控制
公开(公告)号：US05999472A
公开(公告)日：1999-12-07
申请号：US23599
申请日：1998-02-13
申请人： Mikio Sakurai
发明人： Mikio Sakurai
IPC分类号： G11C11/407 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40618 , G11C11/406
摘要： When refresh of a memory bank having a plurality of array banks is instructed, a refresh control circuit carries out the refresh by saving a row address latched in a row address latch circuit and a bank activation signal supplied to a bank drive unit respectively in a row address saving circuit and a bank activating information saving circuit. After the refresh completes, each array bank is returned to its original state before the refresh instruction is supplied, according to the saved row address and bank activate information. Accordingly, a synchronous semiconductor memory device in which the penalty at the time of the refresh is reduced is provided.
摘要翻译：当指示具有多个阵列组的存储体的刷新时，刷新控制电路通过将分别锁存在行地址锁存电路中的行地址和提供给行驱动单元的存储体激活信号分别保存在行中来执行刷新地址保存电路和银行激活信息保存电路。刷新完成后，根据保存的行地址和存储体激活信息，在提供刷新指令之前，每个阵列组都返回到其原始状态。因此，提供了其中减少刷新时的惩罚的同步半导体存储器件。

9. 发明授权

US5973990A Synchronous semiconductor memory device including a circuit for arbitrarily controlling activation/inactivation timing of word line 失效
标题翻译：包括用于任意控制字线的激活/失活定时的电路的同步半导体存储器件
公开(公告)号：US5973990A
公开(公告)日：1999-10-26
申请号：US60311
申请日：1998-04-15
申请人： Mikio Sakurai
发明人： Mikio Sakurai
IPC分类号： G01R31/28 , G01R31/3185 , G11C7/10 , G11C8/12 , G11C11/401 , G11C11/407 , G11C29/50 , G11C8/00
CPC分类号： G11C8/12 , G11C7/1045 , G11C7/1072
摘要： An act signal generation circuit in a synchronous semiconductor memory device includes an act command latch circuit, an act command output circuit, and an act command control circuit. The act command latch circuit latches externally applied active command information. The act command output circuit responds to an enable signal to output an act initiation signal that renders a bank active. The act command control circuit responds to level transition of an external control signal in a test mode to alter the level of the enable signal. As a result, the active command information can be delayed and then transmitted to a bank.
摘要翻译：同步半导体存储器件中的动作信号产生电路包括动作命令锁存电路，动作命令输出电路和动作命令控制电路。动作命令锁存电路锁存外部施加的有效命令信息。动作命令输出电路响应使能信号以输出使存储体活动的动作触发信号。动作指令控制电路在测试模式下响应外部控制信号的电平转换，以改变使能信号的电平。结果，可以延迟活动命令信息，然后将其发送到存储体。

10. 发明授权

US5905690A Synchronous semiconductor device having circuitry capable of surely resetting test mode 失效
标题翻译：具有能够可靠地复位测试模式的电路的同步半导体器件
公开(公告)号：US5905690A
公开(公告)日：1999-05-18
申请号：US058987
申请日：1998-04-13
申请人： Mikio Sakurai , Susumu Tanida , Yasuhiko Tsukikawa , Masaya Nakano , Takahiko Fukiage
发明人： Mikio Sakurai , Susumu Tanida , Yasuhiko Tsukikawa , Masaya Nakano , Takahiko Fukiage
IPC分类号： G11C11/407 , G01R31/317 , G11C11/401 , G11C29/14 , G11C8/00
CPC分类号： G01R31/31701
摘要： A reset signal generating circuit in a synchronous semiconductor memory device outputs a reset signal ZPOR1 in response to a power on reset signal ZPOR generated immediately after power on and an initialize command (for example, a precharge command) executed for initialization after power on. A test mode register included in a mode setting circuit receives as a reset signal, the reset signal ZPOR1. Consequently, a test mode signal output attains to an NOP state, or output of the test mode signal is stopped.
摘要翻译：同步半导体存储装置中的复位信号发生电路响应于上电后立即产生的上电复位信号ZPOR和上电后初始化执行的初始化指令（例如，预充电指令），输出复位信号ZPOR1。包括在模式设置电路中的测试模式寄存器作为复位信号接收复位信号ZPOR1。因此，测试模式信号输出达到NOP状态，或停止测试模式信号的输出。

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