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    • 5. 发明授权
    • Method and system for last gasp device detection
    • 最后一个喘气装置检测方法和系统
    • US09088994B2
    • 2015-07-21
    • US13601692
    • 2012-08-31
    • Dorin ViorelAkira Ito
    • Dorin ViorelAkira Ito
    • H04W24/00H04W74/08H04L29/14
    • H04W74/0841H04L69/40
    • A method is provided for device detection by a base station comprising receiving a plurality of signals over a preamble subframe from an endpoint. The plurality of signals are attempting to access an access group of the preamble subframe. Additionally, the plurality of signals are received on a random access channel using a wireless network. Further, the plurality of signals have a plurality of last gasp messages (LGMs). The method additionally comprises determining an allowable rate of collisions for the plurality of signals and determining an actual rate of collisions for the plurality of signals. The method includes increasing the size of the access group allocated to the plurality of signals having the plurality of LGMs, based on whether the actual rate of collisions exceeds the allowable rate of collisions.
    • 提供了一种用于由基站进行设备检测的方法,包括:从端点通过前导码子帧接收多个信号。 多个信号正试图访问前同步码子帧的接入组。 另外,使用无线网络在随机接入信道上接收多个信号。 此外,多个信号具有多个最后的喘气信息(LGM)。 该方法还包括确定多个信号的可允许冲突率并确定多个信号的实际碰撞速率。 该方法包括:基于实际的冲突率是否超过允许的冲突率,增加分配给具有多个LGM的多个信号的接入组的大小。
    • 6. 发明授权
    • Field transistor structure manufactured using gate last process
    • 使用门最后工艺制造的场晶体管结构
    • US08841674B2
    • 2014-09-23
    • US13174083
    • 2011-06-30
    • Chao-Yang LuGuang-Jye ShiauAkira Ito
    • Chao-Yang LuGuang-Jye ShiauAkira Ito
    • H01L29/78H01L21/28
    • H01L29/7839G11C17/16
    • According to embodiments of the invention, a field transistor structure is provided. The field transistor structure includes a semiconductor substrate, a metal gate, a polycrystalline silicon (polysilicon) layer, and first and second metal portions. The polysilicon layer has first, second, third, and fourth sides and is disposed between the semiconductor substrate on the first side and the metal gate on the second side. The polysilicon layer is also disposed between the first and second metal portions on the third and fourth sides. According to some embodiments of the present invention, the field transistor structure may also include a thin metal layer disposed between the polysilicon layer and the semiconductor substrate. The thin metal layer may be electronically coupled to each of the first and second metal portions.
    • 根据本发明的实施例,提供了场晶体管结构。 场晶体管结构包括半导体衬底,金属栅极,多晶硅(多晶硅)层以及第一和第二金属部分。 多晶硅层具有第一,第二,第三和第四边,并且设置在第一侧的半导体衬底和第二侧上的金属栅极之间。 多晶硅层也设置在第三和第四侧上的第一和第二金属部分之间。 根据本发明的一些实施例,场晶体管结构还可以包括设置在多晶硅层和半导体衬底之间的薄金属层。 薄金属层可以电连接到第一和第二金属部分中的每一个。
    • 9. 发明授权
    • Low mismatch semiconductor device and method for fabricating same
    • 低失配半导体器件及其制造方法
    • US08610221B2
    • 2013-12-17
    • US12657909
    • 2010-01-29
    • Xiangdong ChenAkira Ito
    • Xiangdong ChenAkira Ito
    • H01L27/088
    • H01L21/28H01L27/092H01L29/78
    • Disclosed is a low mismatch semiconductor device that comprises a lightly doped channel region having a first conductivity type and a first dopant concentration in a semiconductor body, and a high-k metal gate stack including a gate metal layer formed over a high-k gate dielectric without having a dielectric cap on the high-k dielectric. The high-k metal gate stack being formed over the lightly doped channel region. The lightly doped channel region may be a P- or N-conductivity region, for example, and may be part of a corresponding P- or N-semiconductor substrate, or a P- or N-well formed in a substrate of the respectively opposite conductivity type. The disclosed semiconductor device, which may be an NMOS or PMOS analog device, for example, can be fabricated as part of an integrated circuit including one or more CMOS logic devices.
    • 公开了一种低失配半导体器件,其包括在半导体本体中具有第一导电类型和第一掺杂剂浓度的轻掺杂沟道区,以及包括形成在高k栅极电介质上的栅极金属层的高k金属栅堆叠 在高k电介质上没有电介质盖。 高k金属栅堆叠形成在轻掺杂沟道区上。 轻掺杂沟道区可以是例如P型或N-导电性区,并且可以是相应的P-或N-半导体衬底的一部分,也可以是在相对的相对的衬底中形成的P-阱或N阱 导电类型。 所公开的半导体器件(其可以是例如NMOS或PMOS模拟器件)可以被制造为包括一个或多个CMOS逻辑器件的集成电路的一部分。