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1. 发明申请

US20030067817A1 Distributed write data drivers for burst access memories 审中-公开
标题翻译：用于突发存取存储器的分布式写入数据驱动程序
公开(公告)号：US20030067817A1
公开(公告)日：2003-04-10
申请号：US10232092
申请日：2002-08-29
申请人： Micron Technology, Inc.
发明人： Todd A. Merritt , Troy A. Manning
IPC分类号： G11C007/00
CPC分类号： G11C7/109 , G06F12/0638 , G06F2212/2022 , G11C7/1021 , G11C7/1024 , G11C7/1027 , G11C7/1039 , G11C7/1045 , G11C7/1048 , G11C7/1078 , G11C7/1096 , G11C7/22 , G11C11/407 , G11C11/4076 , G11C11/4096
摘要： An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.
摘要翻译：集成电路存储器件被设计为执行高速数据写入周期。地址选通信号用于锁存第一个地址。在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。只有在每次突发访问开始时才需要新的内存地址。读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。在脉冲串访问期间读/写控制线的转换用于终止脉冲串访问并初始化该设备以进行另一脉冲串访问。写周期时间最大化以允许突发模式工作频率的增加。阵列读出放大器附近的局部逻辑门用于控制写入数据驱动器，以提供最大的写入时间，而不会在输入/输出线路平衡周期期间交叉电流。通过在数据检测放大器位置局部地选通具有全局平衡信号的全局写使能信号，提供本地写周期控制信号，其基本上对整个周期时间有效，减去突发存取存储器件中的I / O线平衡周期。对于诸如EDO和快速页面模式的非突发模式存储器件，写入功能可以在平衡周期结束后立即开始，以提供最大写入时间，而不会干扰下一个访问周期的地址建立时间。

2. 发明申请

US20020196668A1 Distributed write data drivers for burst access memories 失效
标题翻译：用于突发存取存储器的分布式写入数据驱动程序
公开(公告)号：US20020196668A1
公开(公告)日：2002-12-26
申请号：US10231682
申请日：2002-08-29
申请人： Micron Technology, Inc.
发明人： Todd A. Merritt , Troy A. Manning
IPC分类号： G11C005/00
CPC分类号： G11C7/109 , G06F12/0638 , G06F2212/2022 , G11C7/1021 , G11C7/1024 , G11C7/1027 , G11C7/1039 , G11C7/1045 , G11C7/1048 , G11C7/1078 , G11C7/1096 , G11C7/22 , G11C11/407 , G11C11/4076 , G11C11/4096
摘要： An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near a nay sense amplifiers are used to control write is data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.
摘要翻译：集成电路存储器件被设计为执行高速数据写入周期。地址选通信号用于锁存第一个地址。在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。只有在每次突发访问开始时才需要新的内存地址。读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。在脉冲串访问期间读/写控制线的转换用于终止脉冲串访问并初始化该设备以进行另一脉冲串访问。写周期时间最大化以允许突发模式工作频率的增加。靠近读出放大器的本地逻辑门用于控制写入数据驱动器，以提供最大写入时间，而不会在输入/输出线路平衡周期期间交叉电流。通过在数据检测放大器位置局部地选通具有全局平衡信号的全局写使能信号，提供本地写周期控制信号，其基本上对整个周期时间有效，减去突发存取存储器件中的I / O线平衡周期。对于诸如EDO和快速页面模式的非突发模式存储器件，写入功能可以在平衡周期结束后立即开始，以提供最大写入时间，而不会干扰下一个访问周期的地址建立时间。

3. 发明申请

US20010054928A1 High voltage charge pump circuit 有权
标题翻译：高压电荷泵电路
公开(公告)号：US20010054928A1
公开(公告)日：2001-12-27
申请号：US09922982
申请日：2001-08-06
申请人： Micron Technology, Inc.
发明人： Richard A. Mecier , Todd A. Merritt
IPC分类号： G05F001/10
CPC分类号： H02M3/073
摘要： Charge pump circuits are described that transfer a voltage signal in an output stage without signal-level degradation. Where a voltage signal may cause damage to circuitry or semiconductor breakdown, at least one bypass technique is engaged to inhibit such damage or breakdown.
摘要翻译：描述了在输出级中传送电压信号而没有信号电平降级的电荷泵电路。如果电压信号可能导致电路损坏或半导体击穿，则至少采用一种旁路技术来抑制这种损坏或故障。

4. 发明申请

US20010046148A1 Single deposition layer metal dynamic random access memory 失效
标题翻译：单沉积层金属动态随机存取存储器
公开(公告)号：US20010046148A1
公开(公告)日：2001-11-29
申请号：US09790425
申请日：2001-02-21
申请人： Micron Technology, Inc.
发明人： Todd A. Merritt
IPC分类号： G11C005/02
CPC分类号： G11C5/025 , H01L27/108
摘要： A system and method for forming a memory having at least 16 megabits (224 bits) and only a single deposition layer of highly conductive interconnects. The resulting semiconductor die or chip fits within existing industry-standard packages with little or no speed loss over previous double metal deposition layered DRAM physical architectures. This is accomplished using a die orientation that allows for a fast single metal speed path. The architecture can be easily replicated to provide larger size memory devices. In addition, a method is described for reducing parasitic resistance in an n-sense amplifier.
摘要翻译：一种用于形成具有至少16兆比特（224比特）的存储器的系统和方法，并且仅具有高导电互连的单个沉积层。所得到的半导体管芯或芯片适合现有工业标准封装，与先前的双金属沉积分层DRAM物理架构相比，速度损失很少或没有速度损失。这是通过允许快速的单金属速度路径的管芯取向来实现的。该架构可以轻松复制，以提供更大尺寸的存储设备。此外，描述了一种用于减小n型放大器中的寄生电阻的方法。

5. 发明申请

US20010000654A1 Low power, high speed level shifter 有权
标题翻译：低功率，高速电平转换器
公开(公告)号：US20010000654A1
公开(公告)日：2001-05-03
申请号：US09741368
申请日：2000-12-19
申请人： Micron Technology, Inc.
发明人： Todd A. Merritt , Troy A. Manning
IPC分类号： H03K019/0175
CPC分类号： H03K3/356113 , H03K3/356017
摘要： A voltage level translator is disclosed which translates a CMOS input signal into a CMOS output signal where the low voltage level of the output signal is equal to the high voltage level of the input signal. The voltage level translator is described in an integrated circuit such as memory circuits, including DRAMs. Specifically, the voltage level translator produces an output signal which can be used as a gate voltage on a precharge transistor for a booted circuit where the gate voltage need only drop to the high voltage level of the input signal to shut the transistor off. The voltage level translator described, therefore, reduces the time and power required to translate an input signal by limiting the voltage swing of the output signal.
摘要翻译：公开了一种电压电平转换器，其将CMOS输入信号转换成CMOS输出信号，其中输出信号的低电压电平等于输入信号的高电压电平。在诸如包括DRAM的存储器电路的集成电路中描述了电压电平转换器。具体地，电压电平转换器产生一个输出信号，该输出信号可以用作用于引导电路的预充电晶体管上的栅极电压，其中栅极电压只需要下降到输入信号的高电压电平以关闭晶体管。因此，所描述的电压电平转换器通过限制输出信号的电压摆幅来减少转换输入信号所需的时间和功率。

6. 发明申请

US20030094997A1 Voltage pump and a level translator circuit 失效
标题翻译：电压泵和电平转换电路
公开(公告)号：US20030094997A1
公开(公告)日：2003-05-22
申请号：US10338191
申请日：2003-01-07
申请人： Micron Technology, Inc.
发明人： Greg A. Blodgett , Todd A. Merritt
IPC分类号： G05F001/10
CPC分类号： G11C5/145 , H02M3/07 , H02M3/073
摘要： A voltage pump and method of driving a node to an increased potential. A periodic input signal is fed into a precharged small capacitor to create a level shifted periodic intermediate potential at an intermediate node. The intermediate node is a supply node to a level translator circuit The output of the level translator circuit controls the actuation of a pass transistor. When actuated the pass transistor drives a boosted potential to an output node of the voltage pump circuit. In one embodiment the level translator circuit has a delay element which maintains the deactivation of a pull down portion of the level translator circuit until a pull up portion of the level translator circuit is deactivated. A first diode clamp is used to limit the output of the level translator circuit and the boosted potential to within 1 threshold voltage (of the diode clamp) of each other. A second diode clamp is connected between the terminals of the pass transistor so that the boosted potential does not need to climb above the output potential plus a Vt of the second diode clamp. This in turn limits the gate potential of the transistor through the first diode clamp. In a further embodiment a precharge circuit precharges the first terminal of the transistor to a potential equal to the intermediate potential minus a threshold voltage of the precharge circuit
摘要翻译：一种电压泵和将节点驱动到增加电位的方法。周期性输入信号被馈送到预充电的小电容器中以在中间节点处产生电平移位的周期性中间电位。中间节点是电平转换器电路的电源节点电平转换器电路的输出控制传输晶体管的致动。当致动时，通过晶体管将升压电位驱动到电压泵电路的输出节点。在一个实施例中，电平转换器电路具有延迟元件，其维持电平转换器电路的下拉部分的去激活，直到电平转换器电路的上拉部分被去激活。第一个二极管钳位用于将电平转换器电路的输出和升压电位限制在彼此的二极管钳位电压的1阈值以内。第二个二极管钳位连接在传输晶体管的端子之间，使得升压电位不需要爬升到高于输出电位加上第二二极管钳位的Vt。这又通过第一个二极管钳位来限制晶体管的栅极电位。在另一实施例中，预充电电路将晶体管的第一端子预充电到等于中间电位的电位减去预充电电路的阈值电压

7. 发明申请

US20030002336A1 Distributed write data drivers for burst access memories 审中-公开
公开(公告)号：US20030002336A1
公开(公告)日：2003-01-02
申请号：US10232977
申请日：2002-08-29
申请人： Micron Technology, Inc.
发明人： Todd A. Merritt , Troy A. Manning
IPC分类号： G11C011/34
CPC分类号： G11C7/109 , G06F12/0638 , G06F2212/2022 , G11C7/1021 , G11C7/1024 , G11C7/1027 , G11C7/1039 , G11C7/1045 , G11C7/1048 , G11C7/1078 , G11C7/1096 , G11C7/22 , G11C11/407 , G11C11/4076 , G11C11/4096
摘要： An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.

8. 发明申请

US20020026610A1 Internal guardband for semiconductor testing 有权
公开(公告)号：US20020026610A1
公开(公告)日：2002-02-28
申请号：US09945511
申请日：2001-08-30
申请人： Micron Technology, Inc.
发明人： Todd A. Merritt
IPC分类号： G01R031/28
CPC分类号： H04R23/008 , G01H9/00 , G01R31/31858
摘要： An internal guardband for use in semiconductor testing is disclosed. One aspect of the invention is a semiconductor circuit having two paths. The first path is a standard path, used for normal operation of the circuit. The second path is a test path, used for testing of the circuit. The second, test path adds delay as compared to the first, standard path. This delay acts as an internal guardband for the circuit.

9. 发明申请

US20040133828A1 Compression circuit for testing a momory device 失效
标题翻译：用于测试设备的压缩电路
公开(公告)号：US20040133828A1
公开(公告)日：2004-07-08
申请号：US10712150
申请日：2003-11-13
申请人： MICRON TECHNOLOGY, INC.
发明人： Todd A. Merritt , Nicholas VanHeel
IPC分类号： G11C029/00
CPC分类号： G11C29/40
摘要： An apparatus for testing a memory device having a plurality of data lines includes an input circuit, a compression circuit, and an output circuit. The input circuit is adapted to receive at least a first subset of the data lines and a plurality of enable signals. Each enable signal is associated with at least one of the first subset of data lines. The compression circuit is coupled to the input circuit and is adapted to detect a predetermined pattern on the first subset of data lines. The output circuit is coupled to the compression circuit and adapted to provide at least a pass signal when the predetermined pattern is detected on the first subset of data lines. The input circuit is capable of masking at least one of the first subset of data lines from the compression circuit based on the associated enable signal. A method for testing a memory device having a plurality of data lines includes reading data present on at least a subset of the plurality of data lines. The data associated with at least one data line of the subset is masked. It is determined if the data matches a predetermined pattern. At least a pass signal is provided if the data matches the predetermined pattern.
摘要翻译：一种用于测试具有多条数据线的存储器件的装置，包括输入电路，压缩电路和输出电路。输入电路适于接收数据线的至少第一子集和多个使能信号。每个使能信号与数据线的第一子集中的至少一个相关联。压缩电路耦合到输入电路，并适于检测数据线的第一子集上的预定图案。当在数据线的第一子集上检测到预定模式时，输出电路耦合到压缩电路并适于提供至少一个通过信号。输入电路能够基于相关联的使能信号来屏蔽来自压缩电路的数据线的第一子集中的至少一个。一种用于测试具有多条数据线的存储器件的方法，包括存在于多条数据线的至少一个子集上的数据。与该子集的至少一个数据线相关联的数据被屏蔽。确定数据是否匹配预定模式。如果数据符合预定模式，则至少提供一个通过信号。

10. 发明申请

US20030063502A1 Distributed write data drivers for burst access memories 失效
公开(公告)号：US20030063502A1
公开(公告)日：2003-04-03
申请号：US10232978
申请日：2002-08-29
申请人： Micron Technology, Inc.
发明人： Todd A. Merritt , Troy A. Manning
IPC分类号： G11C007/00
CPC分类号： G11C7/109 , G06F12/0638 , G06F2212/2022 , G11C7/1021 , G11C7/1024 , G11C7/1027 , G11C7/1039 , G11C7/1045 , G11C7/1048 , G11C7/1078 , G11C7/1096 , G11C7/22 , G11C11/407 , G11C11/4076 , G11C11/4096
摘要： An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.

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