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1. 发明申请

US20030117173A1 System and method for improving signal propagation 有权
公开(公告)号：US20030117173A1
公开(公告)日：2003-06-26
申请号：US10357647
申请日：2003-02-04
申请人： Micron Technology, Inc.
发明人： Donald M. Morgan
IPC分类号： H03K019/094
CPC分类号： H04L25/242 , H03K19/01707
摘要： Systems and methods are provided for improving signal propagation. A repeater segments a transmission line into a first and a second line. The repeater includes an inverting amplifier and an equilibration circuit. The inverting amplifier has an input connected to the first line and an output connected to the second line. The amplifier receives and an input signal at a first logic potential and transmits an output signal at an inverted second logic potential during and an active portion of a cycle. The equilibration circuit electrically isolates the first line and the second line and shorts the first line to the second line during and an inactive portion of the cycle. Upon completion of the inactive portion of the cycle, the first line and the second line have substantially equal starting potentials between the first logic potential and the second logic potential. Setting the starting potential between the first and second logic potentials shortens the delay associated with a transition between logic potentials. Additionally, one embodiment of the equilibration circuit selectively disconnects the amplifier from the power rails.

2. 发明申请

US20020097068A1 System and method for improving signal propagation 有权
标题翻译：改善信号传播的系统和方法
公开(公告)号：US20020097068A1
公开(公告)日：2002-07-25
申请号：US09766756
申请日：2001-01-22
申请人： Micron Technology, Inc.
发明人： Donald M. Morgan
IPC分类号： H03K019/0175
CPC分类号： H04L25/242 , H03K19/01707
摘要： Systems and methods are provided for improving signal propagation. A repeater segments a transmission line into a first and a second line. The repeater includes an inverting amplifier and an equilibration circuit. The inverting amplifier has an input connected to the first line and an output connected to the second line. The amplifier receives and an input signal at a first logic potential and transmits an output signal at an inverted second logic potential during and an active portion of a cycle. The equilibration circuit electrically isolates the first line and the second line and shorts the first line to the second line during and an inactive portion of the cycle. Upon completion of the inactive portion of the cycle, the first line and the second line have substantially equal starting potentials between the first logic potential and the second logic potential. Setting the starting potential between the first and second logic potentials shortens the delay associated with a transition between logic potentials. Additionally, one embodiment of the equilibration circuit selectively disconnects the amplifier from the power rails.
摘要翻译：提供了用于改善信号传播的系统和方法。中继器将传输线分割成第一和第二行。中继器包括反相放大器和平衡电路。反相放大器具有连接到第一线路的输入端和连接到第二线路的输出端。放大器接收第一逻辑电位的输入信号，并在循环的有效部分期间以反相的第二逻辑电位发送输出信号。平衡电路将第一线路和第二线路电隔离，并在该周期的非活动部分期间将第一线路短路到第二线路。在完成了该周期的无效部分之后，第一线路和第二线路具有在第一逻辑电位和第二逻辑电位之间具有基本相等的起始电位。设置第一和第二逻辑电位之间的起始电位会缩短与逻辑电位之间的转换相关的延迟。此外，平衡电路的一个实施例选择性地将放大器与电源轨分离。

3. 发明申请

US20030012047A1 Mid array isolate ciucuit layout 有权
标题翻译：中间阵列隔离芯片布局
公开(公告)号：US20030012047A1
公开(公告)日：2003-01-16
申请号：US10229555
申请日：2002-08-28
申请人： Micron Technology, Inc.
发明人： Donald M. Morgan
IPC分类号： G11C005/06
CPC分类号： G11C11/4097 , G11C7/18
摘要： A double pitched array includes isolation devices to divide the array into subarrays, using the same space which is used for bit line twists. This addition allows the one-fourth of the bit line pair which will not be used to propagate signals to not be charged during a memory operation.
摘要翻译：双重阵列包括使用与位线扭曲相同的空间将阵列划分为子阵列的隔离装置。这种添加允许在存储器操作期间将不用于传播信号而不被充电的位线对的四分之一。

4. 发明申请

US20020154566A1 Sending signal through integrated circuit during setup time 有权
标题翻译：在建立时间内通过集成电路发送信号
公开(公告)号：US20020154566A1
公开(公告)日：2002-10-24
申请号：US10174747
申请日：2002-06-18
申请人： Micron Technology, Inc.
发明人： Donald M. Morgan , Todd A. Merritt
IPC分类号： G11C008/00
CPC分类号： G11C7/22 , G11C7/1072 , G11C11/4076
摘要： A memory having a control circuit for initiating a read or a write operation in response to a combination of input signals during a setup time is described. The setup time is a specified time period during which all inputs must remain valid before a next appearance of a rising edge of a clock signal. The control circuit uses the setup time to send a signal from one part of the memory to another part of the memory to avoid the propagation delay time. Further, a circuit is provided which prepares the memory for a write operation prior to the setup time.
摘要翻译：描述了具有用于在建立时间期间响应于输入信号的组合来启动读取或写入操作的控制电路的存储器。建立时间是一个指定的时间段，在此期间，所有输入必须在下一次出现时钟信号的上升沿之前保持有效。控制电路使用建立时间将信号从存储器的一部分发送到存储器的另一部分，以避免传播延迟时间。此外，提供了在建立时间之前准备用于写入操作的存储器的电路。

5. 发明申请

US20010019514A1 Use of setup time to send signal through die 有权
标题翻译：使用建立时间通过模具发送信号
公开(公告)号：US20010019514A1
公开(公告)日：2001-09-06
申请号：US09813274
申请日：2001-03-20
申请人： Micron Technology, Inc.
发明人： Donald M. Morgan , Todd A. Merritt
IPC分类号： G11C008/00
CPC分类号： G11C7/22 , G11C7/1072 , G11C11/4076
摘要： A memory having a control circuit for initiating a read or a write operation in response to a combination of input signals during a setup time is described. The setup time is a specified time period during which all inputs must remain valid before a next appearance of a rising edge of a clock signal. The control circuit uses the setup time to send a signal from one part of the memory to another part of the memory to avoid the propagation delay time. Further, a circuit is provided which prepares the memory for a write operation prior to the setup time.
摘要翻译：描述了具有用于在建立时间期间响应于输入信号的组合来启动读取或写入操作的控制电路的存储器。建立时间是一个指定的时间段，在此期间，所有输入必须在下一次出现时钟信号的上升沿之前保持有效。控制电路使用建立时间将信号从存储器的一部分发送到存储器的另一部分，以避免传播延迟时间。此外，提供了在建立时间之前准备用于写入操作的存储器的电路。

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