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    • 6. 发明授权
    • Audio band signal transmission system and method
    • 音频信号传输系统及方法
    • US06751215B1
    • 2004-06-15
    • US09593325
    • 2000-06-13
    • Takeshi KawanobeToshiya SuganumaMasao AokiHidetoshi Fuse
    • Takeshi KawanobeToshiya SuganumaMasao AokiHidetoshi Fuse
    • H04L1266
    • H04Q11/04H04Q2213/13034H04Q2213/13293H04Q2213/13296H04Q2213/13392
    • An identification number inserting portion 26 in a multiplexing portion 33 in an audio transmission system 10 inserts a connection identification number for own connection into an audio band signal cell which is to be transmitted via an up line 60. An identification number detecting portion 30B detects that the connection identification number is transmitted again from a switching system 1 to the audio transmission system 10 via a down line 70. When an identification number detecting portion 30 confirms based on this detection that a communication path is extended in sequence over 37 the audio transmission system 10, the switching system 1, and the audio transmission system 10”, it controls a slot/channel number converting portion 22 and a change-over switch to correct a routine such that a cell which is to be transmitted the up line 60 in the multiplexing portion 33 can be transmitted to a cell multiplexing portion 34 via a change-over switch 23 on the up line 60, a slot/channel number converting portion 22, and a change-over switch on the down line 70.
    • 在音频传输系统10中的复用部分33中的识别号码插入部分26将用于自身连接的连接识别号码插入将经由上行线路60发送的音频信号信元。识别号码检测部分30B检测到 连接识别号码经由下行线路70从交换系统1再次发送到音频传输系统10.当识别号码检测部分30基于该检测确认通信路径按顺序扩展到37时,音频传输系统 如图10所示,交换系统1和音频传输系统10“,它控制时隙/信道号转换部分22和转换开关,以校正例程,使得将在上行线路60中发送的小区在 多路复用部分33可以经由上行线路60上的转换开关23发送到信元多路复用部分34,时隙/信道编号 r转换部分22和下行线路70上的转换开关。
    • 7. 发明授权
    • FIFO memory device
    • FIFO存储器件
    • US5157633A
    • 1992-10-20
    • US575364
    • 1990-08-30
    • Masao Aoki
    • Masao Aoki
    • G11C7/00G06F5/08
    • G06F5/08
    • An FIFO memory device which is used for digital communication devices and the like comprises a plurality of D-flip flops cascade-connected with each other for storing data; selectors connected between the D-flip flops for selecting an input data or a data to be stored which is outputted from the D-flip flop on the previous stage; and control circuits responsive to a clock signal, a write signal and a read signal for controlling the storing operation of the D-flip flops and the selection operation of the selectors. The control circuit stores a signal representative of presence or absence of data stored in the D-flip flops and performs control in such a manner that an input data is transferred to the D-flip flop on the final stage in which no data has been written for writing the data therein in response to a write signal and that data on respective D-flip flops are simultaneously shifted to the D-flip flop on the subsequent stage on every clock in response to a read signal.