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1. 发明授权

US06774467B2 Semiconductor device and process of production of same 有权
标题翻译：半导体器件及其生产工艺相同
公开(公告)号：US06774467B2
公开(公告)日：2004-08-10
申请号：US09812276
申请日：2001-03-20
申请人： Michio Horiuchi , Takashi Kurihara , Tomio Nagaoka , Masao Aoki , Shigeru Mizuno
发明人： Michio Horiuchi , Takashi Kurihara , Tomio Nagaoka , Masao Aoki , Shigeru Mizuno
IPC分类号： H01L23495
CPC分类号： H01L24/81 , H01L21/561 , H01L21/563 , H01L23/24 , H01L23/3107 , H01L23/3128 , H01L23/49816 , H01L23/4985 , H01L24/29 , H01L24/97 , H01L25/105 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13339 , H01L2224/13347 , H01L2224/16225 , H01L2224/16237 , H01L2224/29111 , H01L2224/2929 , H01L2224/73203 , H01L2224/81801 , H01L2224/83192 , H01L2224/83856 , H01L2224/97 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/0134 , H01L2924/014 , H01L2924/12042 , H01L2924/15153 , H01L2924/15174 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/15747 , H01L2924/1579 , H01L2924/18161 , H01L2924/19041 , H01L2924/3511 , H01L2224/81 , H01L2924/01083 , H01L2924/00 , H01L2924/00014 , H01L2924/0665
摘要： Thin semiconductor device, especially a thin package, which reduces and achieves uniform mounting height, not requiring mounting of individual chips, improves manufacturing yield, without being affected by variation in chip thickness, enables testing alltogether, and process for producing same, the semiconductor mounted with back surface exposed upward, on top of an insulating substrate having throughholes in thickness direction, the area around semiconductor side surfaces being sealed by a resin layer, metal interconnections on the bottom surface of the substrate define bottom portions of throughholes of the substrate, a solder resist layer having throughholes in the thickness direction covers the bottom surface of metal interconnections and substrate, terminals extending downward from the active surface of the semiconductor are inserted into throughholes of the substrate, conductive filler fills gaps between the terminals and the throughholes of the substrate, and connection terminal and interconnections are electrically connected.
摘要翻译：薄型半导体器件，特别是薄封装，其减少并实现均匀的安装高度，而不需要安装单个芯片，提高了制造成品率，而不受芯片厚度变化的影响，能够进行全面测试，以及制造工艺，半导体安装背面向上露出，在厚度方向上具有通孔的绝缘基板的顶部，半导体侧面的周围的区域被树脂层密封，在基板的底面上的金属互连限定了基板的通孔的底部，在厚度方向上具有通孔的阻焊层覆盖金属互连和基板的底面，从半导体的有源表面向下延伸的端子插入到基板的通孔中，导电填料填充端子之间的间隙和基板的通孔，连接终端并且互连电连接。

2. 发明授权

US06849945B2 Multi-layered semiconductor device and method for producing the same 失效
标题翻译：多层半导体器件及其制造方法
公开(公告)号：US06849945B2
公开(公告)日：2005-02-01
申请号：US09881005
申请日：2001-06-14
申请人： Michio Horiuchi , Takashi Kurihara , Shigeru Mizuno
发明人： Michio Horiuchi , Takashi Kurihara , Shigeru Mizuno
IPC分类号： H01L23/12 , H01L23/498 , H01L23/52 , H01L23/538 , H01L25/10 , H01L25/11 , H01L25/18 , H01L23/48
CPC分类号： H01L23/49816 , H01L23/5385 , H01L24/50 , H01L25/105 , H01L2225/1035 , H01L2225/1058 , H01L2924/07802 , H01L2924/00
摘要： To minimize a size of a semiconductor device and reduce a thickness thereof as well as improve the yield and lower the production cost in the production of a semiconductor package, a multi-layered semiconductor device is provided, wherein a film-like semiconductor package (10) incorporating therein a semiconductor chip (12) is disposed in a package accommodation opening (11a) of a circuit pattern layer to form a circuit board. A plurality of such circuit boards are layered together to electrically connect circuit patterns (13) of the circuit boards with each other via a low melting point metal (14) or lead beam bonding (13b).
摘要翻译：为了最小化半导体器件的尺寸并减小其厚度，并且提高了半导体封装的制造中的产量并降低了生产成本，提供了一种多层半导体器件，其中膜状半导体封装（10 ）设置在电路图案层的封装容纳开口（11a）中以形成电路板。多个这样的电路板层叠在一起，通过低熔点金属（14）或引线束接合（13b）将电路板的电路图案（13）彼此电连接。

3. 发明授权

US06518672B2 Multi-layer wiring board substrate and semiconductor device using the multi-layer wiring substrate 有权
标题翻译：多层布线基板和使用多层布线基板的半导体器件
公开(公告)号：US06518672B2
公开(公告)日：2003-02-11
申请号：US09880978
申请日：2001-06-14
申请人： Takashi Kurihara , Michio Horiuchi , Shigeru Mizuno , Yuka Tamadate
发明人： Takashi Kurihara , Michio Horiuchi , Shigeru Mizuno , Yuka Tamadate
IPC分类号： H01L2348
CPC分类号： H05K3/363 , H01L23/49805 , H01L23/4985 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2225/06551 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H05K1/144 , H05K2201/0397 , H05K2201/10681
摘要： A multi-layer wiring substrate comprises: a plurality of wiring substrates, each of the substrates comprising a plate or sheet-like insulating layer and a wiring layer formed on only one of surfaces of the insulating layer; the plurality of wiring substrates being laminated in such a manner that the insulating layer and wiring layer are alternately arranged; at least a pair of said wiring layers arranged on respective surfaces of the insulating layer being electrically connected with each other by means of connecting portions formed so as to pass through the insulating layer; and the connecting portion comprises a part of the wiring layer which is extended into a region of an opening formed so as to pass through said insulating layer and a low-melting point metal disposed in the opening and electrically connecting the part of the wiring layer with a wiring substrate formed on an adjacent insulating layer of the laminated structure.
摘要翻译：多层布线基板包括：多个布线基板，每个基板包括板或片状绝缘层和仅形成在绝缘层的一个表面上的布线层; 所述多个布线基板以使得所述绝缘层和布线层交替布置的方式层叠; 布置在绝缘层的各个表面上的至少一对所述布线层通过形成为穿过绝缘层的连接部彼此电连接; 并且所述连接部分包括延伸到形成为穿过所述绝缘层的开口的区域中的所述布线层的一部分和布置在所述开口中的低熔点金属，并且将所述布线层的所述部分与形成在叠层结构的相邻绝缘层上的布线基板。

4. 发明授权

US06455786B1 Wiring board and manufacturing method thereof and semiconductor device 有权
标题翻译：接线板及其制造方法及半导体器件
公开(公告)号：US06455786B1
公开(公告)日：2002-09-24
申请号：US09539117
申请日：2000-03-30
申请人： Michio Horiuchi , Shigetsugu Muramatsu , Shigeru Mizuno , Takashi Kurihara
发明人： Michio Horiuchi , Shigetsugu Muramatsu , Shigeru Mizuno , Takashi Kurihara
IPC分类号： H05K116
CPC分类号： H01L23/3114 , H01L23/3107 , H01L23/49827 , H01L24/48 , H01L24/97 , H01L2224/05599 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01058 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/351 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A wiring board and electrode of a semiconductor element are connected with each other by the method of wire bonding, and problems arising from the thermal stress generated in the process of mounting are overcome. There is provided a wiring board comprising: a first face joined to an electrode forming face of a semiconductor element 10; and a second face on the opposite side of the first face, a wiring pattern 16 being formed on the second face, a land 24 joined to an external connecting terminal 22 being formed at one end of the wiring pattern, a wire bonding section 16a connected with a bonding wire 40 being formed at the other end of the wiring pattern, wherein the land 24 is supported by a buffer layer 34 for reducing the thermal stress generated when the semiconductor element, to which the wiring board is attached, is mounted via the external connecting terminals, and the wire bonding section 16a is supported by a bonding support layer 36 having an elastic modulus capable of allowing wire bonding.
摘要翻译：半导体元件的布线基板和电极通过引线接合的方式相互连接，克服了在安装过程中产生的热应力引起的问题。提供了一种布线板，包括：连接到半导体元件10的电极形成面的第一面; 和在第一面的相对侧的第二面，形成在第二面上的布线图案16，形成在布线图案的一端的与外部连接端子22接合的台面24，连接有引线接合部16a 其中接合线40形成在布线图案的另一端，其中，台肩24由缓冲层34支撑，用于减小当安装有布线板的半导体元件经由外部连接端子和引线接合部分16a由具有能够引线接合的弹性模量的接合支撑层36支撑。

5. 发明授权

US06407460B1 Multilayer circuit board 有权
标题翻译：多层电路板
公开(公告)号：US06407460B1
公开(公告)日：2002-06-18
申请号：US09616139
申请日：2000-07-13
申请人： Michio Horiuchi , Shigeru Mizuno
发明人： Michio Horiuchi , Shigeru Mizuno
IPC分类号： H01L2352
CPC分类号： H01L23/49838 , H01L2224/16 , H01L2224/16235 , H01L2924/15174 , H01L2924/15311 , H05K1/112 , H05K2201/09227 , H05K2201/10734
摘要： The present invention provides a multilayer circuit board for mounting thereon a semiconductor chip or other electronic elements having electrode terminals or other connection terminals which are arranged in a grid, staggered, or close-packed manner in an improved form to enable reduction in the number of the wiring layers for lead wiring lines, thereby facilitating the production of multilayer circuit boards and providing an improved product reliability. The multilayer circuit board comprises: a base board having a mounting surface for mounting thereon a semiconductor chip and/or other electronic elements having lattice-arranged connection terminals; connection terminal pads arranged on the mounting surface to form a plane lattice corresponding to the lattice arrangement of the connection terminals and having lattice sites each occupied by one of the connection terminal pads; lead wiring lines lying on the mounting surface and having one end connected to the connection terminal pads and the other end extending outwardly from the plane lattice; and the said plane lattice having a peripheral zone including periodic vacant lattice areas formed by vacant lattice sites occupied by no connection terminal pads.
摘要翻译：本发明提供了一种多层电路板，用于在其上安装半导体芯片或具有电极端子或其他连接端子的其他电子元件，电子端子或其他连接端子以改进的形式布置成格栅，交错或紧密堆叠的方式，以减少数量用于引线布线的布线层，从而便于生产多层电路板并提供改进的产品可靠性。多层电路板包括：基板，其具有用于安装其上的半导体芯片的安装表面和/或具有格子排列的连接端子的其它电子元件; 连接端子焊盘，其布置在所述安装表面上以形成与所述连接端子的格栅布置相对应的平面格子，并具有各自由所述连接端子焊盘之一占据的格子部位; 引线布线位于安装表面上，其一端连接到连接端子焊盘，另一端从平面格架向外延伸; 并且所述平面晶格具有包括由没有连接端子焊盘占据的空位网格形成的周期性空格格区域的周边区域。

6. 发明授权

US07750484B2 Semiconductor device with flip-chip connection that uses gallium or indium as bonding material 有权
标题翻译：具有使用镓或铟作为接合材料的倒装芯片连接的半导体器件
公开(公告)号：US07750484B2
公开(公告)日：2010-07-06
申请号：US12146003
申请日：2008-06-25
申请人： Shigeru Mizuno , Takashi Kurihara
发明人： Shigeru Mizuno , Takashi Kurihara
IPC分类号： H01L23/498
CPC分类号： H01L24/81 , H01L2224/1134 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/73204 , H01L2224/81193 , H01L2224/81203 , H01L2224/81405 , H01L2224/81825 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/3511 , H01L2924/00 , H01L2924/00014
摘要： A method of manufacturing a semiconductor device in which a semiconductor element 10 is mounted on a substrate 20 through a flip-chip connection, includes the steps of cladding gallium as a bonding material 30 to a connecting pad 22 formed on a surface of the substrate 20, diffusing copper from the connecting pad 22 formed of the copper into the bonding material 30 through heating under vacuum, thereby bringing a state of a solid solution of the gallium and the copper, and aligning a connecting bump 12 formed on the semiconductor element 10 with the connecting pad 22 and bonding the connecting bump 12 to the connecting pad 22 through the bonding material 30 in a state of a solid solution under heating.
摘要翻译：通过倒装芯片连接将半导体元件10安装在基板20上的半导体器件的制造方法包括以下步骤：将形成在基板20的表面上的连接焊盘22作为接合材料30包覆镓通过在真空下加热将铜从铜连接焊盘22扩散到接合材料30中，从而使镓和铜的固溶状态，并使形成在半导体元件10上的连接凸块12与形成在半导体元件10上的连接凸块12与连接焊盘22，并且在加热下处于固溶状态下，通过接合材料30将连接凸块12接合到连接焊盘22。

7. 发明申请

US20090001571A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090001571A1
公开(公告)日：2009-01-01
申请号：US12146003
申请日：2008-06-25
申请人： Shigeru Mizuno , Takashi Kurihara
发明人： Shigeru Mizuno , Takashi Kurihara
IPC分类号： H01L23/488 , H01L21/60
CPC分类号： H01L24/81 , H01L2224/1134 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/73204 , H01L2224/81193 , H01L2224/81203 , H01L2224/81405 , H01L2224/81825 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/3511 , H01L2924/00 , H01L2924/00014
摘要： A method of manufacturing a semiconductor device in which a semiconductor element 10 is mounted on a substrate 20 through a flip-chip connection, includes the steps of cladding gallium as a bonding material 30 to a connecting pad 22 formed on a surface of the substrate 20, diffusing copper from the connecting pad 22 formed of the copper into the bonding material 30 through heating under vacuum, thereby bringing a state of a solid solution of the gallium and the copper, and aligning a connecting bump 12 formed on the semiconductor element 10 with the connecting pad 22 and bonding the connecting bump 12 to the connecting pad 22 through the bonding material 30 in a state of a solid solution under heating.
摘要翻译：通过倒装芯片连接将半导体元件10安装在基板20上的半导体器件的制造方法包括以下步骤：将形成在基板20的表面上的连接焊盘22作为接合材料30包覆镓通过在真空下加热将铜从铜连接焊盘22扩散到接合材料30中，从而使镓和铜的固溶状态，并使形成在半导体元件10上的连接凸块12与形成在半导体元件10上的连接凸块12与连接焊盘22，并且在加热下处于固溶状态下，通过接合材料30将连接凸块12接合到连接焊盘22。

8. 发明授权

US07807561B2 Method for forming side wirings 有权
标题翻译：形成侧面布线的方法
公开(公告)号：US07807561B2
公开(公告)日：2010-10-05
申请号：US12175650
申请日：2008-07-18
申请人： Shigeru Mizuno , Takashi Kurihara , Akinori Shiraishi , Kei Murayama , Mitsutoshi Higashi
发明人： Shigeru Mizuno , Takashi Kurihara , Akinori Shiraishi , Kei Murayama , Mitsutoshi Higashi
IPC分类号： H01L21/44
CPC分类号： H01L24/85 , H01L21/6835 , H01L24/24 , H01L24/45 , H01L24/48 , H01L24/78 , H01L24/82 , H01L25/0657 , H01L2224/24145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48465 , H01L2224/48471 , H01L2224/76152 , H01L2224/78 , H01L2224/85001 , H01L2225/06551 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/30105 , H01L2924/00 , H01L2224/4554
摘要： After plural semiconductor elements are stacked to form a stacked body P, side wirings are formed on the side surface of the stacked body P, thereby manufacturing a semiconductor apparatus in which the respective semiconductor elements are electrically connected to one another. In this case, as the semiconductor element, a semiconductor element 10 is employed in which a gold wire 16 with its one end connected to an electrode terminal of the semiconductor element is extended out to the side surface. A conductive paste 36 containing conductive particles applied over a predetermined length of a transferring wire 30 is transferred to the side surface of the stacked body P so that the gold wires 16 extended out to the side surfaces of the semiconductor elements 10, 10, 10 are connected, thereby forming the side wirings.
摘要翻译：在堆叠多个半导体元件以形成堆叠体P之后，在层叠体P的侧表面上形成侧布线，从而制造其中各个半导体元件彼此电连接的半导体器件。在这种情况下，作为半导体元件，采用半导体元件10，其一端与半导体元件的电极端子连接的金线16延伸到侧面。包含施加在传输线30的预定长度上的导电颗粒的导电膏36被转移到层叠体P的侧表面，使得延伸到半导体元件10,10,10的侧表面的金线16 连接，从而形成侧面布线。

9. 发明授权

US07777349B2 Semiconductor apparatus having side surface wiring 有权
标题翻译：具有侧面布线的半导体装置
公开(公告)号：US07777349B2
公开(公告)日：2010-08-17
申请号：US12175689
申请日：2008-07-18
申请人： Kei Murayama , Shigeru Mizuno , Takashi Kurihara , Akinori Shiraishi , Mitsutoshi Higashi
发明人： Kei Murayama , Shigeru Mizuno , Takashi Kurihara , Akinori Shiraishi , Mitsutoshi Higashi
IPC分类号： H01L23/48
CPC分类号： H01L29/0657 , H01L21/6835 , H01L24/24 , H01L24/45 , H01L24/48 , H01L24/78 , H01L24/82 , H01L24/85 , H01L24/91 , H01L25/0657 , H01L2224/24145 , H01L2224/45144 , H01L2224/48091 , H01L2224/4813 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48599 , H01L2224/73265 , H01L2224/76152 , H01L2224/78301 , H01L2224/85001 , H01L2224/85181 , H01L2225/06551 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/10157 , H01L2924/30105 , H01L2924/00 , H01L2224/4554 , H01L2224/85399 , H01L2224/05599
摘要： A plurality of quadrilateral-shaped semiconductor elements are stacked on the one surface of a circuit substrate. A side surface wiring for making electrical connection between each of the electrode terminals of the semiconductor elements and a pad formed on the circuit substrate is formed by applying a conductive paste containing conductive particles. A metal wire whose one end is connected to the electrode terminal is extended along a tapered surface formed by cutting off an edge of the electrode terminal surface on which the electrode terminal is formed among edges formed along each of the sides of the semiconductor element. At least a part of the metal wire extended from each of the electrode terminals of the semiconductor elements to the tapered surface is electrically connected to the side surface wiring.
摘要翻译：多个四边形半导体元件堆叠在电路基板的一个表面上。通过涂布含有导电性粒子的导电性糊料，形成用于在半导体元件的各电极端子与电路基板上形成的焊盘之间进行电连接的侧面配线。其一端连接到电极端子的金属线沿着沿着半导体元件的每一侧形成的边缘之间切割形成有电极端子的电极端子表面的边缘的锥形表面延伸。从半导体元件的每个电极端子延伸到锥形表面的金属线的至少一部分电连接到侧面布线。

10. 发明授权

US06974721B2 Method for manufacturing thin semiconductor chip 失效
标题翻译：薄半导体芯片制造方法
公开(公告)号：US06974721B2
公开(公告)日：2005-12-13
申请号：US10496690
申请日：2003-08-28
申请人： Naoyuki Koizumi , Kei Murayama , Shigeru Mizuno , Takashi Kurihara
发明人： Naoyuki Koizumi , Kei Murayama , Shigeru Mizuno , Takashi Kurihara
IPC分类号： H01L21/301 , H01L21/00 , H01L21/02 , H01L21/68 , H01L21/78 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/6835 , H01L21/67092 , H01L21/67132 , H01L21/6836 , H01L21/78 , H01L24/27 , H01L2221/68327 , H01L2221/68336 , H01L2221/6834 , H01L2224/274 , H01L2924/01019 , H01L2924/01029 , H01L2924/01079 , H01L2924/12042 , H01L2924/3512 , H01L2924/00
摘要： In manufacturing a thin semiconductor chip, a wafer is stably held during processing to maintain a stable shape and to avoid generation of cracks on the wafer. When a thin wafer having a surface thereon is to be processed, a rigid support body is adhered to the other surface of the thin wafer and a ring-shaped frame, encircling an outer periphery of the thin wafer, is adhered to the rigid support body.
摘要翻译：在制造薄的半导体芯片时，晶片在加工过程中被稳定地保持以保持稳定的形状并且避免在晶片上产生裂纹。当要处理其上具有表面的薄晶片时，刚性支撑体粘附到薄晶片的另一个表面，并且围绕薄晶片的外周的环形框架被粘附到刚性支撑体。

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