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1. 发明授权

US5572702A Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency 失效
公开(公告)号：US5572702A
公开(公告)日：1996-11-05
申请号：US202790
申请日：1994-02-28
申请人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14
CPC分类号： G06F12/0831 , G06F12/0833 , G06F13/1668
摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.

2. 发明授权

US5909699A Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency 失效
标题翻译：用于支持对存储器进行读取，写入和无效操作的方法和装置，其保持缓存一致性
公开(公告)号：US5909699A
公开(公告)日：1999-06-01
申请号：US672422
申请日：1996-06-28
申请人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14
CPC分类号： G06F12/0831 , G06F12/0833 , G06F13/1668
摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.
摘要翻译：总线上代理发出的内存请求在保持缓存一致性的同时得到满足。请求代理可以通过将请求放在总线上向另一代理或存储器单元发出请求。总线上的每个代理都会窥探总线，以确定是否可以通过访问其缓存来满足发出的请求。可以使用其缓存来满足请求的代理，即窥探代理，向请求代理发出指示这样的信号。侦听代理将与请求相对应的高速缓存行放置在由请求代理检索到的总线上。在读取请求的情况下，存储器单元还从总线检索高速缓存线数据，并将高速缓存行存储在主存储器中。在写请求的情况下，请求代理随着请求传送总线上的写数据。该写入数据由临时存储数据的存储单元和监听代理二者检索。随后，窥探代理通过总线传输整个高速缓存行。存储器单元检索该高速缓存线，将其与先前存储的写数据合并，并将合并的高速缓存行写入存储器。

3. 发明授权

US5797026A Method and apparatus for self-snooping a bus during a boundary transaction 失效
标题翻译：在边界交易过程中自动侦听总线的方法和装置
公开(公告)号：US5797026A
公开(公告)日：1998-08-18
申请号：US921845
申请日：1997-09-02
申请人： Michael W. Rhodehamel , Nitin V. Sarangdhar , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Michael W. Rhodehamel , Nitin V. Sarangdhar , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0831
摘要： A self-snooping mechanism for enabling a processor being coupled to dedicated cache memory and a processor-system bus to snoop its own request issued on the processor-system bus. The processor-system bus enables communication between the processor and other bus agents such as a memory subsystem, I/O subsystem and/or other processors. The self-snooping mechanism is commenced upon determination that the request is based on a boundary condition so that initial internal cache lookup is bypassed to improve system efficiency.
摘要翻译：一种用于使处理器耦合到专用高速缓存存储器和处理器系统总线的自侦听机制，以窥探其在处理器系统总线上发出的自身请求。处理器系统总线实现处理器与其它总线代理（例如存储器子系统，I / O子系统和/或其他处理器）之间的通信。自我侦听机制在确定请求是基于边界条件的情况下开始，以便绕过初始内部高速缓存查找以提高系统效率。

4. 发明授权

US5682516A Computer system that maintains system wide cache coherency during deferred communication transactions 失效
标题翻译：计算机系统在延迟通信事务期间维持系统级缓存一致性
公开(公告)号：US5682516A
公开(公告)日：1997-10-28
申请号：US205023
申请日：1994-03-01
申请人： Nitin V. Sarangdhar , Wen Han Wang , Michael W. Rhodehamel , James M. Brayton , Amit Merchant , Matthew A. Fisch
发明人： Nitin V. Sarangdhar , Wen Han Wang , Michael W. Rhodehamel , James M. Brayton , Amit Merchant , Matthew A. Fisch
IPC分类号： G06F12/08 , G06F13/368 , H04L29/06 , G06F13/18
CPC分类号： G06F12/0831 , G06F13/368 , H04L29/06 , G06F12/0813
摘要： A computer system is disclosed having a requesting bus agent that issues a communication transaction over a bus and an addressed bus agent that defers the communication transaction to avoid high bus latency. The addressed bus agent later issues a deferred reply transaction over the bus to complete the communication transaction. Special snoop ownership and cache state transition rules maintain cache coherency and processor consistency during deferred communication transactions.
摘要翻译：公开了一种计算机系统，其具有通过总线发布通信事务的请求总线代理和用于延迟通信事务以避免高总线等待时间的寻址总线代理。所处理的总线代理商随后通过总线发出延迟回复交易，以完成通信交易。特殊侦听所有权和缓存状态转换规则在延迟通信事务期间保持缓存一致性和处理器一致性。

5. 发明授权

US5784579A Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth 失效
标题翻译：基于总线管线深度从总线代理动态控制总线访问的方法和装置
公开(公告)号：US5784579A
公开(公告)日：1998-07-21
申请号：US709214
申请日：1996-09-06
申请人： Stephen S. Pawlowski , Nitin V. Sarangdhar , Michael W. Rhodehamel , Matthew A. Fisch , Peter D. MacWilliams
发明人： Stephen S. Pawlowski , Nitin V. Sarangdhar , Michael W. Rhodehamel , Matthew A. Fisch , Peter D. MacWilliams
IPC分类号： G06F13/38 , G06F13/40 , G06F13/42
CPC分类号： G06F13/387 , G06F13/4027 , G06F13/4217
摘要： A dynamic pipeline depth control method and apparatus is used with a bus which supports pipelined bus transactions. An agent coupled to the bus includes both a transmitter and a receiver. The transmitter is used to transmit an indication to the other agents coupled to the bus which prevents the other agents from issuing a transaction on the bus. The receiver is used to receive the indication, from another agent, that prevents the agent from issuing a transaction on the bus.
摘要翻译：动态流水线深度控制方法和装置与支持流水线总线事务的总线一起使用。耦合到总线的代理包括发射机和接收机。发射机用于向耦合到总线的其他代理发送指示，防止其他代理在总线上发出交易。接收机用于从另一代理接收指示，阻止代理在总线上发出交易。

6. 发明授权

US5778441A Method and apparatus for accessing split lock variables in a computer system 失效
标题翻译：用于访问计算机系统中的分裂锁定变量的方法和装置
公开(公告)号：US5778441A
公开(公告)日：1998-07-07
申请号：US764663
申请日：1996-12-11
申请人： Michael W. Rhodehamel , Nitin V. Sarangdhar , Matthew A. Fisch
发明人： Michael W. Rhodehamel , Nitin V. Sarangdhar , Matthew A. Fisch
IPC分类号： G06F13/16 , G06F12/00 , G06F13/00
CPC分类号： G06F13/1652
摘要： Atomicity of lock variables is preserved in a computer system in response to a request by a microprocessor for a bus lock access whether the lock variable is split between two cache lines or is within a single cache line. A non-split lock bus access which can be satisfied by a cacheable region within the same cluster as the microprocessor issuing the access is allowed to complete, regardless of whether ownership of the next level bus is available. If the non-split lock access can not be satisfied within the cluster, then ownership of the next level bus is obtained, if available, to satisfy the access. Similarly, a split lock access may complete if ownership of the second level bus can be obtained. However, a split lock access is aborted if the second level bus ownership is not available, regardless of whether a cacheable region within the same cluster can satisfy the request.
摘要翻译：响应于微处理器对于总线锁定访问的请求，锁定变量的原子性被保留在计算机系统中，无论锁定变量是在两个高速缓存行之间分离还是在单个高速缓存行内。允许通过与发出访问的微处理器相同的集群内的可缓存区域来满足的非分裂锁总线访问，而不管下一级总线的所有权是否可用。如果在集群内不能满足非分裂锁访问，则获得下一级总线的所有权（如果可用）以满足访问。类似地，如果可以获得第二级总线的所有权，则分裂锁定访问可以完成。但是，如果第二级总线所有权不可用，则无论同一个集群中的可缓存区域是否满足请求，则会中断拆分锁访问。

7. 发明授权

US5581782A Computer system with distributed bus arbitration scheme for symmetric and priority agents 失效
标题翻译：具有分布式总线仲裁方案的计算机系统，用于对称和优先代理
公开(公告)号：US5581782A
公开(公告)日：1996-12-03
申请号：US538597
申请日：1995-10-03
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Michael W. Rhodehamel , Matthew A. Fisch
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Michael W. Rhodehamel , Matthew A. Fisch
IPC分类号： G06F13/36 , G06F13/364 , H04L12/403 , G06F13/18
CPC分类号： G06F13/364 , G06F13/36 , H04L12/403 , H04L12/4015
摘要： A system and method for providing a high performance symmetric arbitration protocol that includes support for priority agents. The bus arbitration protocol supports two classes of bus agents: symmetric agents and priority agents. The symmetric agents support fair, distributed arbitration using a round-robin algorithm. Each symmetric agent has a unique Agent ID assigned at reset. The algorithm arranges the symmetric agents in a circular order of priority. Each symmetric agent also maintains a bus ownership state of busy or idle and a Rotating ID that reflects the symmetric agent with the lowest priority in the next arbitration event. On an arbitration event, the symmetric agent with the highest priority becomes the symmetric owner. However, the symmetric owner is not necessarily the overall bus owner (i.e., a priority agent may be the overall bus owner). The symmetric owner is allowed to take ownership of the bus and issue a transaction on the bus provided no other action of higher priority is preventing the use of the bus. A symmetric owner can maintain ownership without re-arbitrating if the transaction is either a bus-locked or a burst access transaction. The priority agent(s) has higher priority than the symmetric owner. Once the priority agent arbitrates for the bus, it prevents the symmetric owner from issuing any new transactions on the bus unless the new transaction is part of an ongoing bus-locked operation.
摘要翻译：一种用于提供包括对优先代理的支持的高性能对称仲裁协议的系统和方法。总线仲裁协议支持两类总线代理：对称代理和优先代理。对称代理使用循环算法支持公平的分布式仲裁。每个对称代理都具有在复位时分配的唯一代理ID。该算法按照循环顺序排列对称代理。每个对称代理还维持忙或空闲的总线所有权状态以及在下一个仲裁事件中反映具有最低优先级的对称代理的旋转ID。在仲裁事件中，优先级最高的对称代理成为对称所有者。然而，对称所有者不一定是总线总线所有者（即，优先代理可以是总线总线所有者）。允许对称所有者获得公共汽车的所有权，并在公共汽车上发出交易，只要没有更高优先级的其他动作阻止使用公共汽车。如果事务是总线锁定或突发访问事务，对称所有者可以维护所有权而不重新仲裁。优先级代理的优先级高于对称所有者。一旦优先级代理对总线进行仲裁，就可以防止对称所有者在总线上发出任何新的事务，除非新的事务是持续的总线锁定操作的一部分。

8. 发明授权

US6006299A Apparatus and method for caching lock conditions in a multi-processor system 失效
标题翻译：用于在多处理器系统中缓存锁定条件的装置和方法
公开(公告)号：US6006299A
公开(公告)日：1999-12-21
申请号：US204592
申请日：1994-03-01
申请人： Wen-Hann Wang , Konrad K. Lai , Gurbir Singh , Mandar S. Joshi , Nitin V. Sarangdhar , Matthew A. Fisch
发明人： Wen-Hann Wang , Konrad K. Lai , Gurbir Singh , Mandar S. Joshi , Nitin V. Sarangdhar , Matthew A. Fisch
IPC分类号： G06F9/46 , G06F13/08
CPC分类号： G06F9/52
摘要： In a computer system, an apparatus for handling lock conditions wherein a first instruction executed by a first processor processes data that is common to a second processor while the second processor is locked from simultaneously executing a second instruction that also processes this same data. A lock bit is set when the first processor begins execution of the first instruction. Thereupon, the second processor is prevented from executing its instruction until the first processor has completed its processing of the shared data. Hence, the second processor queues its request in a buffer. The lock bit is cleared after the first processor has completed execution of its instruction. The first processor then checks the buffer for any outstanding requests. In response to the second processor's queued request, the first processor transmits a signal to the second processor indicating that the data is now not locked.
摘要翻译：在计算机系统中，一种用于处理锁定条件的装置，其中由第一处理器执行的第一指令在第二处理器被锁定时处理与第二处理器相同的数据，同时执行也处理该相同数据的第二指令。当第一个处理器开始执行第一个指令时，锁定位被置位。于是，第二处理器被阻止执行其指令，直到第一处理器完成对共享数据的处理。因此，第二处理器将其请求排队在缓冲器中。在第一个处理器完成其指令执行后，锁定位被清零。然后，第一个处理器检查缓冲区是否有任何未完成的请求。响应于第二处理器的排队请求，第一处理器向第二处理器发送指示数据现在不被锁定的信号。

9. 发明授权

US5774700A Method and apparatus for determining the timing of snoop windows in a pipelined bus 失效
标题翻译：用于确定流水线总线中的窥探窗口的定时的方法和装置
公开(公告)号：US5774700A
公开(公告)日：1998-06-30
申请号：US425370
申请日：1995-04-20
申请人： Matthew A. Fisch , Nitin V. Sarangdhar
发明人： Matthew A. Fisch , Nitin V. Sarangdhar
IPC分类号： G06F12/08 , G06F1/04
CPC分类号： G06F12/0831
摘要： A method and apparatus for determining the timing of snoop windows in a pipelined bus includes a snoop timer, a snoop counter, and snoop resolution logic. The snoop timer indicates the number of clocks until the next snoop window. The snoop counter keeps track of the number of snoop windows currently being tracked by the apparatus and is updated by the snoop resolution logic. In one embodiment, the snoop resolution logic updates the snoop counter when a snoop event occurs on the bus. In one embodiment, the apparatus also includes snoop drive logic which drives snoop result signals onto the bus during snoop windows.
摘要翻译：用于确定流水线总线中的窥探窗口的定时的方法和装置包括窥探定时器，窥探计数器和窥探分辨率逻辑。监听定时器指示下一个监听窗口之前的时钟数。窥探计数器跟踪当前由设备跟踪的窥探窗口的数量，并由窥探分辨率逻辑更新。在一个实施例中，当在总线上发生窥探事件时，窥探分辨率逻辑更新窥探计数器。在一个实施例中，该装置还包括窥探驱动逻辑，其在窥探窗口期间将窥探结果信号驱动到总线上。

10. 发明授权

US5845107A Signaling protocol conversion between a processor and a high-performance system bus 失效
标题翻译：处理器与高性能系统总线之间的信号协议转换
公开(公告)号：US5845107A
公开(公告)日：1998-12-01
申请号：US675679
申请日：1996-07-03
申请人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
发明人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
IPC分类号： G06F13/36 , G06F12/08 , G06F13/364 , G06F15/76
CPC分类号： G06F13/364
摘要： A method of operation in a computer system having a host processor, a pipelined system bus, and at least one agent, all of which operate in accordance with a first signaling protocol, and a processor that is included in a subsystem that operates according to a second signaling protocol which is incompatible with the first signaling protocol. The method comprises the steps of converting arbiter signals generated by the subsystem processor from the second signaling protocol to the first signaling protocol of the pipelined bus to obtain ownership of the pipelined bus. Next, an outgoing request encoding of the processor is translated from the second signaling protocol to the first signaling protocol. Finally, generating a bus cycle on the pipelined bus from the translated outgoing request encoding in accordance with the first signaling protocol of the pipelined bus.
摘要翻译：一种具有主处理器，流水线系统总线和至少一个代理的计算机系统中的操作方法，所有这些代理都按照第一信令协议进行操作，并且处理器包括在根据第二信令协议与第一信令协议不兼容。该方法包括以下步骤：将由子系统处理器产生的仲裁信号从第二信令协议转换为流水线总线的第一信令协议以获得流水线总线的所有权。接下来，将处理器的输出请求编码从第二信令协议转换为第一信令协议。最后，根据流水线总线的第一信令协议从流水线总线生成总线循环，根据翻译的输出请求编码。

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