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1. 发明授权

US5845107A Signaling protocol conversion between a processor and a high-performance system bus 失效
标题翻译：处理器与高性能系统总线之间的信号协议转换
公开(公告)号：US5845107A
公开(公告)日：1998-12-01
申请号：US675679
申请日：1996-07-03
申请人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
发明人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
IPC分类号： G06F13/36 , G06F12/08 , G06F13/364 , G06F15/76
CPC分类号： G06F13/364
摘要： A method of operation in a computer system having a host processor, a pipelined system bus, and at least one agent, all of which operate in accordance with a first signaling protocol, and a processor that is included in a subsystem that operates according to a second signaling protocol which is incompatible with the first signaling protocol. The method comprises the steps of converting arbiter signals generated by the subsystem processor from the second signaling protocol to the first signaling protocol of the pipelined bus to obtain ownership of the pipelined bus. Next, an outgoing request encoding of the processor is translated from the second signaling protocol to the first signaling protocol. Finally, generating a bus cycle on the pipelined bus from the translated outgoing request encoding in accordance with the first signaling protocol of the pipelined bus.
摘要翻译：一种具有主处理器，流水线系统总线和至少一个代理的计算机系统中的操作方法，所有这些代理都按照第一信令协议进行操作，并且处理器包括在根据第二信令协议与第一信令协议不兼容。该方法包括以下步骤：将由子系统处理器产生的仲裁信号从第二信令协议转换为流水线总线的第一信令协议以获得流水线总线的所有权。接下来，将处理器的输出请求编码从第二信令协议转换为第一信令协议。最后，根据流水线总线的第一信令协议从流水线总线生成总线循环，根据翻译的输出请求编码。

2. 发明授权

US5896513A Computer system providing a universal architecture adaptive to a variety of processor types and bus protocols 失效
标题翻译：计算机系统提供了适用于各种处理器类型和总线协议的通用架构
公开(公告)号：US5896513A
公开(公告)日：1999-04-20
申请号：US675723
申请日：1996-07-03
申请人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
发明人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
IPC分类号： G06F13/16 , G06F13/18 , G06F13/36 , G06F13/40 , G06F13/14
CPC分类号： G06F13/4027 , G06F13/4063
摘要： A computer system providing a universal architecture includes a processor card connected to a system bus of a host computer system. The processor card is adapted for insertion into a slot of the computer system and houses a processor and a bus bridge conversion device. The processor operates according to a signaling protocol which is different than the signaling protocol of the computer system bus. The bus conversion device converts the signaling protocol of the system bus to the signaling protocol of the processor, and vice-versa. The bus conversion device includes logic for bus arbitration conversion, bus lock conversion, and cache coherency control. Logic is also included that converts incoming and outgoing requests so that the card may properly transact with other agents coupled to the bus.
摘要翻译：提供通用架构的计算机系统包括连接到主计算机系统的系统总线的处理器卡。处理器卡适于插入到计算机系统的插槽中并且容纳处理器和总线桥转换装置。处理器根据与计算机系统总线的信令协议不同的信令协议进行操作。总线转换装置将系统总线的信令协议转换为处理器的信令协议，反之亦然。总线转换装置包括用于总线仲裁转换，总线锁转换和高速缓存一致性控制的逻辑。还包括逻辑，可转换传入和传出的请求，以便卡可以与耦合到总线的其他代理进行正确的交互。

3. 发明授权

US5764934A Processor subsystem for use with a universal computer architecture 失效
标题翻译：处理器子系统，用于通用计算机体系结构
公开(公告)号：US5764934A
公开(公告)日：1998-06-09
申请号：US675854
申请日：1996-07-03
申请人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
发明人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
IPC分类号： G06F13/36 , G06F13/38 , G06F13/40 , G06F13/42 , G06F15/76
CPC分类号： G06F13/4027
摘要： A processor subsystem includes a processor and a bus bridge conversion device for insertion into a slot of a host computer system. The processor operates according to a signaling protocol which is different than the signaling protocol of the computer system bus. The bus conversion device converts the signaling protocol of the system bus to the signaling protocol of the processor, and vice-versa. The bus conversion device includes logic for bus arbitration conversion, bus lock conversion, and cache coherency control. Logic is also included that converts incoming and outgoing requests so that the card may properly transact with other agents coupled to the bus.
摘要翻译：处理器子系统包括用于插入到主计算机系统的时隙中的处理器和总线桥转换装置。处理器根据与计算机系统总线的信令协议不同的信令协议进行操作。总线转换装置将系统总线的信令协议转换为处理器的信令协议，反之亦然。总线转换装置包括用于总线仲裁转换，总线锁转换和高速缓存一致性控制的逻辑。还包括逻辑，可转换传入和传出的请求，以便卡可以与耦合到总线的其他代理进行正确的交互。

4. 发明授权

US5572702A Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency 失效
公开(公告)号：US5572702A
公开(公告)日：1996-11-05
申请号：US202790
申请日：1994-02-28
申请人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14
CPC分类号： G06F12/0831 , G06F12/0833 , G06F13/1668
摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.

5. 发明授权

US5909699A Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency 失效
标题翻译：用于支持对存储器进行读取，写入和无效操作的方法和装置，其保持缓存一致性
公开(公告)号：US5909699A
公开(公告)日：1999-06-01
申请号：US672422
申请日：1996-06-28
申请人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14
CPC分类号： G06F12/0831 , G06F12/0833 , G06F13/1668
摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.
摘要翻译：总线上代理发出的内存请求在保持缓存一致性的同时得到满足。请求代理可以通过将请求放在总线上向另一代理或存储器单元发出请求。总线上的每个代理都会窥探总线，以确定是否可以通过访问其缓存来满足发出的请求。可以使用其缓存来满足请求的代理，即窥探代理，向请求代理发出指示这样的信号。侦听代理将与请求相对应的高速缓存行放置在由请求代理检索到的总线上。在读取请求的情况下，存储器单元还从总线检索高速缓存线数据，并将高速缓存行存储在主存储器中。在写请求的情况下，请求代理随着请求传送总线上的写数据。该写入数据由临时存储数据的存储单元和监听代理二者检索。随后，窥探代理通过总线传输整个高速缓存行。存储器单元检索该高速缓存线，将其与先前存储的写数据合并，并将合并的高速缓存行写入存储器。

6. 发明授权

US5797026A Method and apparatus for self-snooping a bus during a boundary transaction 失效
标题翻译：在边界交易过程中自动侦听总线的方法和装置
公开(公告)号：US5797026A
公开(公告)日：1998-08-18
申请号：US921845
申请日：1997-09-02
申请人： Michael W. Rhodehamel , Nitin V. Sarangdhar , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Michael W. Rhodehamel , Nitin V. Sarangdhar , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0831
摘要： A self-snooping mechanism for enabling a processor being coupled to dedicated cache memory and a processor-system bus to snoop its own request issued on the processor-system bus. The processor-system bus enables communication between the processor and other bus agents such as a memory subsystem, I/O subsystem and/or other processors. The self-snooping mechanism is commenced upon determination that the request is based on a boundary condition so that initial internal cache lookup is bypassed to improve system efficiency.
摘要翻译：一种用于使处理器耦合到专用高速缓存存储器和处理器系统总线的自侦听机制，以窥探其在处理器系统总线上发出的自身请求。处理器系统总线实现处理器与其它总线代理（例如存储器子系统，I / O子系统和/或其他处理器）之间的通信。自我侦听机制在确定请求是基于边界条件的情况下开始，以便绕过初始内部高速缓存查找以提高系统效率。

7. 发明授权

US5682516A Computer system that maintains system wide cache coherency during deferred communication transactions 失效
标题翻译：计算机系统在延迟通信事务期间维持系统级缓存一致性
公开(公告)号：US5682516A
公开(公告)日：1997-10-28
申请号：US205023
申请日：1994-03-01
申请人： Nitin V. Sarangdhar , Wen Han Wang , Michael W. Rhodehamel , James M. Brayton , Amit Merchant , Matthew A. Fisch
发明人： Nitin V. Sarangdhar , Wen Han Wang , Michael W. Rhodehamel , James M. Brayton , Amit Merchant , Matthew A. Fisch
IPC分类号： G06F12/08 , G06F13/368 , H04L29/06 , G06F13/18
CPC分类号： G06F12/0831 , G06F13/368 , H04L29/06 , G06F12/0813
摘要： A computer system is disclosed having a requesting bus agent that issues a communication transaction over a bus and an addressed bus agent that defers the communication transaction to avoid high bus latency. The addressed bus agent later issues a deferred reply transaction over the bus to complete the communication transaction. Special snoop ownership and cache state transition rules maintain cache coherency and processor consistency during deferred communication transactions.
摘要翻译：公开了一种计算机系统，其具有通过总线发布通信事务的请求总线代理和用于延迟通信事务以避免高总线等待时间的寻址总线代理。所处理的总线代理商随后通过总线发出延迟回复交易，以完成通信交易。特殊侦听所有权和缓存状态转换规则在延迟通信事务期间保持缓存一致性和处理器一致性。

8. 发明授权

US5901297A Initialization mechanism for symmetric arbitration agents 失效
标题翻译：对称仲裁机构的初始化机制
公开(公告)号：US5901297A
公开(公告)日：1999-05-04
申请号：US974750
申请日：1997-11-19
申请人： Matthew A. Fisch , Michael W. Rhodehamel , Nitin Sarangdhar
发明人： Matthew A. Fisch , Michael W. Rhodehamel , Nitin Sarangdhar
IPC分类号： G06F15/00 , G06F9/02 , G06F13/36 , G06F13/362 , G06F13/374 , G06F15/16
CPC分类号： G06F13/362 , G06F13/374
摘要： An initialization mechanism for symmetric arbitration agents ensures that multiple agents on a bus are each initialized with a different arbitration counter value. The arbitration counter of each bus agent is used to keep track of which agent was the last or current owner of the bus and which agent will be the next owner of the bus. All bus agents agree on which agent will be the priority agent at system reset and thus be allowed first ownership of the bus. Each agent's arbitration counter is initialized according to each agent's own agent identification. The arbitration pins of the bus agents are interconnected such that each agent determines for itself a unique agent identification based on which pin of its arbitration pins is active at system reset and the maximum number of bus agents allowed on the bus. After determining its agent identification, each bus agent initializes its arbitration counter such that every agent agrees which agent is the priority agent. Each agent performs this initialization based on its agent identification, the identity of the priority agent, and the maximum number of agents allowed on the bus.
摘要翻译：对称仲裁代理的初始化机制确保总线上的多个代理各自以不同的仲裁计数器值进行初始化。每个总线代理人的仲裁柜台用于跟踪哪个代理人是公交车的最后或当前所有者，哪个代理人将是公共汽车的下一个所有者。所有总线代理商都同意在系统复位时哪个代理将是优先代理，从而允许首先拥有总线。每个代理的仲裁计数器根据每个代理人的代理身份进行初始化。总线代理的仲裁引脚相互连接，使得每个代理人自身可以根据其仲裁引脚的哪个引脚在系统复位时被激活，并在总线上允许的总线代理的最大数量来确定唯一的代理识别。在确定其代理身份后，每个总线代理人初始化其仲裁柜台，以便每个代理商同意哪个代理机构是优先代理。每个代理根据其代理标识，优先级代理的身份以及总线上允许的代理的最大数量来执行此初始化。

9. 发明授权

US5784579A Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth 失效
标题翻译：基于总线管线深度从总线代理动态控制总线访问的方法和装置
公开(公告)号：US5784579A
公开(公告)日：1998-07-21
申请号：US709214
申请日：1996-09-06
申请人： Stephen S. Pawlowski , Nitin V. Sarangdhar , Michael W. Rhodehamel , Matthew A. Fisch , Peter D. MacWilliams
发明人： Stephen S. Pawlowski , Nitin V. Sarangdhar , Michael W. Rhodehamel , Matthew A. Fisch , Peter D. MacWilliams
IPC分类号： G06F13/38 , G06F13/40 , G06F13/42
CPC分类号： G06F13/387 , G06F13/4027 , G06F13/4217
摘要： A dynamic pipeline depth control method and apparatus is used with a bus which supports pipelined bus transactions. An agent coupled to the bus includes both a transmitter and a receiver. The transmitter is used to transmit an indication to the other agents coupled to the bus which prevents the other agents from issuing a transaction on the bus. The receiver is used to receive the indication, from another agent, that prevents the agent from issuing a transaction on the bus.
摘要翻译：动态流水线深度控制方法和装置与支持流水线总线事务的总线一起使用。耦合到总线的代理包括发射机和接收机。发射机用于向耦合到总线的其他代理发送指示，防止其他代理在总线上发出交易。接收机用于从另一代理接收指示，阻止代理在总线上发出交易。

10. 发明授权

US5778441A Method and apparatus for accessing split lock variables in a computer system 失效
标题翻译：用于访问计算机系统中的分裂锁定变量的方法和装置
公开(公告)号：US5778441A
公开(公告)日：1998-07-07
申请号：US764663
申请日：1996-12-11
申请人： Michael W. Rhodehamel , Nitin V. Sarangdhar , Matthew A. Fisch
发明人： Michael W. Rhodehamel , Nitin V. Sarangdhar , Matthew A. Fisch
IPC分类号： G06F13/16 , G06F12/00 , G06F13/00
CPC分类号： G06F13/1652
摘要： Atomicity of lock variables is preserved in a computer system in response to a request by a microprocessor for a bus lock access whether the lock variable is split between two cache lines or is within a single cache line. A non-split lock bus access which can be satisfied by a cacheable region within the same cluster as the microprocessor issuing the access is allowed to complete, regardless of whether ownership of the next level bus is available. If the non-split lock access can not be satisfied within the cluster, then ownership of the next level bus is obtained, if available, to satisfy the access. Similarly, a split lock access may complete if ownership of the second level bus can be obtained. However, a split lock access is aborted if the second level bus ownership is not available, regardless of whether a cacheable region within the same cluster can satisfy the request.
摘要翻译：响应于微处理器对于总线锁定访问的请求，锁定变量的原子性被保留在计算机系统中，无论锁定变量是在两个高速缓存行之间分离还是在单个高速缓存行内。允许通过与发出访问的微处理器相同的集群内的可缓存区域来满足的非分裂锁总线访问，而不管下一级总线的所有权是否可用。如果在集群内不能满足非分裂锁访问，则获得下一级总线的所有权（如果可用）以满足访问。类似地，如果可以获得第二级总线的所有权，则分裂锁定访问可以完成。但是，如果第二级总线所有权不可用，则无论同一个集群中的可缓存区域是否满足请求，则会中断拆分锁访问。

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