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1. 发明授权

US06463032B1 Network switching system having overflow bypass in internal rules checker 有权
标题翻译：网络交换系统在内部规则检查器中具有溢出旁路
公开(公告)号：US06463032B1
公开(公告)日：2002-10-08
申请号：US09238047
申请日：1999-01-27
申请人： Michael Vengchong Lau , Shashank C. Merchant , John M. Chiang
发明人： Michael Vengchong Lau , Shashank C. Merchant , John M. Chiang
IPC分类号： H04L1254
CPC分类号： H04L49/9078 , H04L49/205 , H04L49/3027 , H04L49/351 , H04L49/90 , H04L49/901
摘要： A novel method of overflow data handling in a multiport data switching system having a decision making engine for controlling data forwarding between receive ports and at least one transmit port. Data blocks representing received data packets are placed in data queues corresponding to the receive ports. The data queues are transferred to logic circuitry for processing in accordance with a prescribed algorithm. Then, a forwarding decision is made to determine the transmit port. An overflow bypass is provided to allow at least a portion of a data block to bypass the logic circuitry, when at least one of the data queues is in an overflow state. For example, pointers indicating memory locations for storing the corresponding received data packets may be transferred via the overflow bypass when the overflow state is detected.
摘要翻译：一种具有用于控制接收端口与至少一个发送端口之间的数据转发的决策引擎的多端口数据交换系统中的溢出数据处理的新颖方法。表示接收到的数据分组的数据块被放置在对应于接收端口的数据队列中。数据队列被传送到逻辑电路，以根据规定的算法进行处理。然后，进行转发决定以确定发送端口。当至少一个数据队列处于溢出状态时，提供溢出旁路以允许数据块的至少一部分绕过逻辑电路。例如，当检测到溢出状态时，指示用于存储对应的接收数据分组的存储器位置的指针可以经由溢出旁路传送。

2. 发明授权

US06335938B1 Multiport communication switch having gigaport and expansion ports sharing the same time slot in internal rules checker 有权
标题翻译：具有端口和扩展端口的多端口通信交换机在内部规则检查器中共享相同的时隙
公开(公告)号：US06335938B1
公开(公告)日：2002-01-01
申请号：US09304959
申请日：1999-05-05
申请人： John M. Chiang , Michael VengChong Lau , Shashank Merchant
发明人： John M. Chiang , Michael VengChong Lau , Shashank Merchant
IPC分类号： H04J316
CPC分类号： H04L49/45 , H04L49/1553 , H04L49/201 , H04L49/30 , H04L49/3009 , H04L49/352 , H04L49/354
摘要： A novel method of data processing in a multiport data switching system having a decision making engine for controlling data forwarding between receive ports and at least one transmit port. The receive ports include an expansion port for receiving data packets from another switching system, and a high-speed port for receiving data packets at a rate higher than data rates at regular receive ports. In accordance with the method of the present invention, data blocks representing received data packets are placed in a plurality of data queues corresponding to the plurality of the receive ports. The data queues are transferred in successive time slots to logic circuitry for determining at least one transmit port. The time slots assigned to each of the plurality of receive ports includes expansion port time slots assigned to the expansion port and high-speed time slots assigned to the high-speed port. The expansion and high-speed time slots are dynamically distributed between the expansion and high-speed ports in accordance with relative data traffic at the ports. In particular, non-requested high-speed port time slots may be allocated to the expansion port, if the number of requests for high-speed port time slots is less than the number of the high-speed time slots. Similarly, non-requested expansion port time slots may be allocated to the high-speed port, if the number of requests for expansion port time slots is less than the number of the expansion port time slots.
摘要翻译：一种具有用于控制接收端口与至少一个发送端口之间的数据转发的决策引擎的多端口数据交换系统中的数据处理的新颖方法。接收端口包括用于从另一交换系统接收数据分组的扩展端口和用于以高于常规接收端口的数据速率的速率接收数据分组的高速端口。根据本发明的方法，将表示接收到的数据分组的数据块放置在对应于多个接收端口的多个数据队列中。数据队列在连续的时隙中传送到用于确定至少一个发送端口的逻辑电路。分配给多个接收端口中的每一个的时隙包括分配给扩展端口的扩展端口时隙和分配给高速端口的高速时隙。根据端口上的相对数据流量，扩展和高速时隙在扩展端口和高速端口之间动态分配。特别地，如果高速端口时隙的请求数小于高速时隙的数量，则可以向扩展端口分配非请求的高速端口时隙。类似地，如果扩展端口时隙的请求数少于扩展端口时隙的数量，则可以将未请求的扩展端口时隙分配给高速端口。

3. 发明授权

US07991296B1 Method and apparatus for data frame synchronization and delineation 有权
标题翻译：用于数据帧同步和描绘的方法和装置
公开(公告)号：US07991296B1
公开(公告)日：2011-08-02
申请号：US11938019
申请日：2007-11-09
申请人： Cesar A. Johnston , John M. Chiang
发明人： Cesar A. Johnston , John M. Chiang
IPC分类号： H04B10/00 , H04J14/00
CPC分类号： H04J3/0608
摘要： A circuit and method to synchronize with a data transmission having a plurality of data transmission frames each with a start boundary identified by a predetermined synchronization pattern, includes comparing sets of data within the data transmission to a predetermined synchronization pattern. A frame tracking signal is assigned to each one of the plurality of comparison results that indicates a match between a data pattern within one of the plurality of sets of data and the predetermined synchronization pattern, including matches that occur multiple times within a known duration of the data transmission frame duration. Based on each frame tracking signal assigned to a comparison result, the start boundary of the data transmission frames is searched. The start boundary may be search by monitoring successive occurrences of the predetermined synchronization pattern in the data transmission at intervals of the known data transmission frame duration for each data matching data pattern. If the predetermined synchronization pattern occurs successively in the data transmission, the associated data pattern is confirmed as the synchronization pattern in the data transmission, and synchronization with the data transmission is achieved.
摘要翻译：一种与具有多个数据传输帧的数据传输同步的电路和方法，每个数据传输帧具有由预定的同步模式识别的起始边界，包括将数据传输中的数据集合与预定的同步模式进行比较。帧跟踪信号被分配给多个比较结果中的每一个，其指示多个数据集合中的一个数据和预定同步模式之间的数据模式之间的匹配，包括在所述多个比较结果的已知持续时间内发生多次的匹配数据传输帧持续时间。基于分配给比较结果的每个帧跟踪信号，搜索数据传输帧的起始边界。可以通过以每个数据匹配数据模式的已知数据传输帧持续时间的间隔监视数据传输中的预定同步模式的连续出现来搜索起始边界。如果在数据传输中连续发生预定同步模式，则在数据传输中确认相关联的数据模式作为同步模式，并实现与数据传输的同步。

4. 发明授权

US06813266B1 Pipelined access to address table in a network switch 有权
标题翻译：流水线访问网络交换机中的地址表
公开(公告)号：US06813266B1
公开(公告)日：2004-11-02
申请号：US09315851
申请日：1999-05-21
申请人： John M. Chiang , Shashank Merchant
发明人： John M. Chiang , Shashank Merchant
IPC分类号： H04L1228
CPC分类号： H04L12/5601 , H04L49/108 , H04L2012/5624 , H04L2012/5652 , H04L2012/5679 , H04L2012/568 , H04L2012/5681
摘要： A network switch configured for switching data packets across multiple ports uses decision making logic to generate frame forwarding information. The decision making logic employs a pipelined architecture that enables multiple data frames to be processed simultaneously to increase data throughput. The decision making logic also pipelines access to an address lookup table that stores the data forwarding information. An arbitration circuit provides the decision making device with automatic access to the address table in alternate time slots and also enables other circuits to access the address table in predetermined time slots.
摘要翻译：配置为跨多个端口切换数据包的网络交换机使用决策逻辑生成帧转发信息。决策逻辑采用流水线架构，可以同时处理多个数据帧，从而提高数据吞吐量。决策逻辑还可以访问存储数据转发信息的地址查找表。仲裁电路为决策设备提供在备用时隙中对地址表的自动访问，并且使得其他电路能够在预定时隙中访问地址表。

5. 发明授权

US06501734B1 Apparatus and method in a network switch for dynamically assigning memory interface slots between gigabit port and expansion port 有权
标题翻译：网络交换机中的装置和方法，用于在千兆端口和扩展端口之间动态分配存储器接口槽
公开(公告)号：US06501734B1
公开(公告)日：2002-12-31
申请号：US09317150
申请日：1999-05-24
申请人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
发明人： Ching Yu , Xiaohua Zhuang , Bahadir Erimli , John M. Chiang , Shashank Merchant , Robert Williams , Edward Yang , Chandan Egbert , Vallath Nandakumar , Ian Lam , Eric Tsin-Ho Leung
IPC分类号： H04J116
CPC分类号： H04L49/103 , H04L49/254 , H04L49/3027 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/90 , H04L49/901
摘要： A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol dynamically allocates external memory bandwidth slots between high data rate ports. An external memory interface determines if a high data rate port makes a request for a bandwidth slot and grants the request if made. The slot is taken from a selected group which is a subset of the total number of slots. If a request for the slot is not made, the external memory interface assigns the slot to another high data rate port. Lower data rate ports in the network switch are assigned fixed slots from those slots not from within the selected group of slots. The dynamic allocation of bandwidth slots between the high data rate port enables the efficient use of limited memory bandwidth resources.
摘要翻译：具有根据以太网（IEEE 802.3）协议的具有各个网络节点的数据分组全双工通信的交换机端口的网络交换机动态地在高数据速率端口之间分配外部存储器带宽时隙。外部存储器接口确定高数据速率端口是否对带宽槽进行请求，如果发出请求则确定该请求。时隙是从所选择的组中获取的，该组是总时隙数的子集。如果没有对插槽进行请求，则外部存储器接口将插槽分配给另一个高数据速率端口。网络交换机中的较低数据速率端口从这些时隙中分配固定时隙，而不是在所选择的时隙组内。高数据速率端口之间的带宽时隙的动态分配使得能够有效地利用有限的存储器带宽资源。

6. 发明授权

US06445709B1 Method and apparatus for finding a match entry using receive port number embedded in the port vector 有权
标题翻译：使用嵌入在端口向量中的接收端口号来找到匹配条目的方法和装置
公开(公告)号：US06445709B1
公开(公告)日：2002-09-03
申请号：US09311367
申请日：1999-05-13
申请人： John M. Chiang
发明人： John M. Chiang
IPC分类号： H04L1256
CPC分类号： H04L49/354 , H04L12/4645 , H04L12/467 , H04L49/205 , H04L49/3009 , H04L49/3027 , H04L49/351
摘要： A network switch configured for switching data packets across multiple ports uses an address table to generated frame forwarding information. The switch receives frame information including a source address and destination address along with a virtual local area network (VLAN) ID, if applicable. A decision-making engine searches a network address table to “learn” Medium Access Control (MAC) addresses without having to store receive port numbers by embedding the receive port number in the stored port vector fields.
摘要翻译：配置为跨多个端口切换数据包的网络交换机使用地址表来生成帧转发信息。如果适用，交换机接收包括源地址和目的地址以及虚拟局域网（VLAN）ID的帧信息。决策引擎搜索网络地址表以“学习”媒体访问控制（MAC）地址，而不必通过将接收端口号嵌入存储的端口向量域中来存储接收端口号。

7. 发明授权

US08913895B1 Method and apparatus for controlling timing of a transmission signal from a network termination device 有权
标题翻译：用于控制来自网络终端设备的传输信号的定时的方法和装置
公开(公告)号：US08913895B1
公开(公告)日：2014-12-16
申请号：US13523610
申请日：2012-06-14
申请人： John M. Chiang , Cesar A. Johnston
发明人： John M. Chiang , Cesar A. Johnston
IPC分类号： H04B10/40
CPC分类号： H04J3/0682 , H04J3/0694 , H04Q11/0067 , H04Q2011/0079
摘要： In a method for controlling timing of a transmission signal from a network termination device having a receiver and a transmitter, a signal is received at the receiver of the network termination device, the signal having been transmitted in accordance with a predetermined bit rate. A core clock signal for the receiver is determined based on the predetermined bit rate at which the signal was transmitted, and the core clock signal is communicated to the transmitter of the network termination device. At the transmitter of the network termination device, a phase adjusted clock signal is generated, and the phase adjusted clock signal is set as the transmitter clock signal. The transmitter clock signal is offset from the core clock signal, and the transmission signal is transmitted from the transmitter of the network termination device based on the transmitter clock signal.
摘要翻译：在用于控制来自具有接收机和发射机的网络终端装置的发送信号的定时的方法中，在网络终端装置的接收机处接收信号，该信号已经根据预定的比特率被发送。基于发送信号的预定比特率来确定用于接收机的核心时钟信号，并且将核心时钟信号传送到网络终端设备的发射机。在网络终端装置的发射机处，生成相位调整后的时钟信号，将相位调整后的时钟信号设定为发射机时钟信号。发射机时钟信号与核心时钟信号偏移，并且发射信号基于发射机时钟信号从网络终端装置的发射机发射。

8. 发明授权

US08718087B1 Processing architecture for passive optical network 失效
标题翻译：无源光网络处理架构
公开(公告)号：US08718087B1
公开(公告)日：2014-05-06
申请号：US11877379
申请日：2007-10-23
申请人： Cesar A. Johnston , John M. Chiang
发明人： Cesar A. Johnston , John M. Chiang
IPC分类号： H04L12/66
CPC分类号： H04L12/12 , Y02D50/40
摘要： In a network termination device integrated circuit in a point-to-multipoint network, a receiver receives a downstream transmission from a line termination unit within the point-to-multipoint network, a transmitter transmits an upstream transmission to the line termination unit within the point-to-multipoint network, and an internal processor operatively coupled to the receiver processes sub-fields within the overhead field of the downstream transmission. The internal processor is also operatively coupled to the transmitter to assemble the overhead field of the upstream transmission. The downstream transmission is an downstream transmission convergence frame format having an overhead field and a payload field, and the upstream transmission is an upstream transmission convergence frame format having an overhead field and a payload field.
摘要翻译：在点对多点网络中的网络终端设备集成电路中，接收器从点对多点网络中的线路终端单元接收下行传输，发射机将该上行传输发送到该点到多点网络内的线路终端单元以及可操作地耦合到所述接收机的内部处理器处理所述下行传输的开销字段内的子域。内部处理器还可操作地耦合到发射机以组合上行传输的开销字段。下行传输是具有开销字段和有效载荷字段的下行传输会聚帧格式，上行传输是具有开销字段和有效载荷字段的上行传输会聚帧格式。

9. 发明授权

US08208815B1 Bit accurate upstream burst transmission phase method for reducing burst data arrival variation 有权
标题翻译：用于减少突发数据到达变化的位精确上行脉冲串传输相位方法
公开(公告)号：US08208815B1
公开(公告)日：2012-06-26
申请号：US11948575
申请日：2007-11-30
申请人： John M. Chiang , Cesar A. Johnston
发明人： John M. Chiang , Cesar A. Johnston
IPC分类号： H04B10/00
CPC分类号： H04J3/0682 , H04J3/0694 , H04Q11/0067 , H04Q2011/0079
摘要： In a method for controlling timing of an upstream from an optical network termination device to an optical line termination device, a downstream transmission is analyzed to determine a core clock rate for the termination device. The core clock signal is then used to determine a transmitter clock signal to be used for upstream transmission, where the transmitter clock signal is offset from the core clock signal. The offset transmitter clock signal may be determined in the receiver or in the transmitter of the termination device and by a delay lock loop or by a clock data recovery/generator circuitry. For example, the transmitter clock signal may be taken from a plurality of phase adjusted clock offset signals created by the clock data recovery/generator circuitry during identification of the core clock signal.
摘要翻译：在用于控制从光网络终端设备到光线路终端设备的上游的定时的方法中，分析下行传输以确定终端设备的核心时钟速率。核心时钟信号然后用于确定要用于上行传输的发射机时钟信号，其中发射机时钟信号偏离核心时钟信号。偏移发射机时钟信号可以在终端设备的接收机或发射机中以及延迟锁定环路或时钟数据恢复/发生器电路中确定。例如，在核心时钟信号的识别期间，发射机时钟信号可以取自由时钟数据恢复/发生器电路产生的多个相位调整的时钟偏移信号。

10. 发明授权

US07983308B1 Method and apparatus for data frame synchronization 有权
标题翻译：用于数据帧同步的方法和装置
公开(公告)号：US07983308B1
公开(公告)日：2011-07-19
申请号：US11939513
申请日：2007-11-13
申请人： Cesar A. Johnston , John M. Chiang
发明人： Cesar A. Johnston , John M. Chiang
IPC分类号： H04J3/06 , H04L7/00 , H04B10/00
CPC分类号： H04J3/0608 , H04L7/033 , H04Q11/0067 , H04Q2011/0083
摘要： A circuit to synchronize with a data transmission includes a comparator to read a set of data within a serialized data transmission, compare the set of data to a predetermined data pattern and output a comparison result. For a serialized data transmission, the comparator receives the serialized transmission and a shift register serially coupled to the comparator to hold the data pattern. A synchronization detector receives a comparison hit vector based on the comparison result from the comparator and aligns a boundary of a data frame according to the comparison hit vector if the comparison hit vector indicates a match between the data pattern in the set of data and the predetermined data pattern. For a deserialized data transmission, each stage of a multistage shift register read a set of data from the deserialized data transmission and selectively outputs the set of data to a comparator which compares each set to a predetermined data pattern and output a comparison result. A synchronization detector receives the comparison result from the comparator and aligns a boundary of a data frame according to the comparison result if the comparison result indicates a match between a data pattern sub-set within a combined data pattern and the predetermined data pattern, where the sets of deserialized data comprise the combined data pattern.
摘要翻译：与数据传输同步的电路包括比较器，用于读取串行化数据传输中的一组数据，将该组数据与预定数据模式进行比较并输出比较结果。对于串行数据传输，比较器接收串行化传输和串行耦合到比较器的移位寄存器以保持数据模式。同步检测器基于来自比较器的比较结果接收比较命中矢量，如果比较命中矢量指示数据组中的数据模式与预定的数据模式之间的匹配，则根据比较命中向量对齐数据帧的边界数据模式。对于反序列化数据传输，多级移位寄存器的每一级从反序列化数据传输中读取一组数据，并选择性地将该组数据输出到比较器，该比较器将每组与预定数据模式进行比较并输出比较结果。如果比较结果指示组合数据模式中的数据模式子集与预定数据模式之间的匹配，则同步检测器从比较器接收比较结果并根据比较结果对准数据帧的边界，其中反序列化数据集包括组合数据模式。

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