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1. 发明授权

US08859388B2 Sealed shallow trench isolation region 有权
标题翻译：密封浅沟槽隔离区
公开(公告)号：US08859388B2
公开(公告)日：2014-10-14
申请号：US13548237
申请日：2012-07-13
申请人： Michael V. Aquilino , Xiang Hu , Daniel J. Jaeger , Byeong Y. Kim , Yong M. Lee , Ying Li , Reinaldo A. Vega
发明人： Michael V. Aquilino , Xiang Hu , Daniel J. Jaeger , Byeong Y. Kim , Yong M. Lee , Ying Li , Reinaldo A. Vega
IPC分类号： H01L29/06 , H01L29/66 , H01L21/8234
CPC分类号： H01L21/823437 , H01L21/76224 , H01L29/66621
摘要： A method for formation of a sealed shallow trench isolation (STI) region for a semiconductor device includes forming a STI region in a substrate, the STI region comprising a STI fill; forming a sealing recess in the STI fill of the STI region; and forming a sealing layer in the sealing recess over the STI fill.
摘要翻译：用于形成用于半导体器件的密封浅沟槽隔离（STI）区域的方法包括在衬底中形成STI区域，所述STI区域包括STI填充物; 在STI区域的STI填充物中形成密封凹槽; 以及在所述STI填充物上的所述密封凹槽中形成密封层。

2. 发明申请

US20140015092A1 SEALED SHALLOW TRENCH ISOLATION REGION 有权
标题翻译：密封沙滩隔离区
公开(公告)号：US20140015092A1
公开(公告)日：2014-01-16
申请号：US13548237
申请日：2012-07-13
申请人： Michael V. Aquilino , Xiang Hu , Daniel J. Jaeger , Byeong Y. Kim , Yong M. Lee , Ying Li , Reinaldo A. Vega
发明人： Michael V. Aquilino , Xiang Hu , Daniel J. Jaeger , Byeong Y. Kim , Yong M. Lee , Ying Li , Reinaldo A. Vega
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/823437 , H01L21/76224 , H01L29/66621
摘要： A method for formation of a sealed shallow trench isolation (STI) region for a semiconductor device includes forming a STI region in a substrate, the STI region comprising a STI fill; forming a sealing recess in the STI fill of the STI region; and forming a sealing layer in the sealing recess over the STI fill.
摘要翻译：用于形成用于半导体器件的密封浅沟槽隔离（STI）区域的方法包括在衬底中形成STI区域，所述STI区域包括STI填充物; 在STI区域的STI填充物中形成密封凹槽; 以及在所述STI填充物上的所述密封凹槽中形成密封层。

3. 发明授权

US09035430B2 Semiconductor fin on local oxide 有权
标题翻译：半导体翅片局部氧化物
公开(公告)号：US09035430B2
公开(公告)日：2015-05-19
申请号：US13597799
申请日：2012-08-29
申请人： Reinaldo A. Vega , Michael V. Aquilino , Daniel J. Jaeger
发明人： Reinaldo A. Vega , Michael V. Aquilino , Daniel J. Jaeger
IPC分类号： H01L21/02 , H01L21/308 , H01L21/32 , H01L21/762 , H01L29/66 , H01L29/78
CPC分类号： H01L21/76281 , H01L21/3081 , H01L21/3086 , H01L21/32 , H01L21/76208 , H01L29/66795 , H01L29/785
摘要： A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins. The first semiconductor material can be selected from materials more easily oxidized relative to the second semiconductor material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer.
摘要翻译：提供了包括第一外延半导体层的半导体衬底。第一外延半导体层包括第一半导体材料，并且可以形成在下面的外延衬底层上，或者可以是整个半导体衬底。包含第二半导体材料的第二外延半导体层外延地形成在第一外延半导体层上。包括第二单晶半导体材料的部分的半导体翅片通过使用第一外延半导体层作为蚀刻停止层的第二外延半导体层图案化而形成。至少第一外延半导体层的上部被氧化以提供电绝缘半导体鳍片的局部氧化物层。第一半导体材料可以从相对于第二半导体材料更容易氧化的材料中选择，以在形成局部氧化物层之后为半导体翅片提供均匀的高度。

4. 发明授权

US08623713B2 Trench isolation structure 有权
标题翻译：沟槽隔离结构
公开(公告)号：US08623713B2
公开(公告)日：2014-01-07
申请号：US13233058
申请日：2011-09-15
申请人： Michael V. Aquilino , Reinaldo A. Vega
发明人： Michael V. Aquilino , Reinaldo A. Vega
IPC分类号： H01L21/336 , H01L29/78 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/66636 , H01L21/76232 , H01L21/823814 , H01L21/823878 , H01L29/1083 , H01L29/165 , H01L29/66628 , H01L29/7834 , H01L29/7846 , H01L29/7848
摘要： A trench isolation structure and method of forming the trench isolation structure are disclosed. The method includes forming a shallow trench isolation (STI) structure having an overhang and forming a gate stack. The method further includes forming source and drain recesses adjacent to the STI structure and the gate stack. The source and drain recesses are separated from the STI structure by substrate material. The method further includes forming epitaxial source and drain regions associated with the gate stack by filling the source and drain recesses with stressor material.
摘要翻译：公开了形成沟槽隔离结构的沟槽隔离结构和方法。该方法包括形成具有突出端并形成栅叠层的浅沟槽隔离（STI）结构。该方法还包括形成与STI结构和栅极堆叠相邻的源极和漏极凹部。源极和漏极凹槽通过衬底材料与STI结构分离。该方法还包括通过用应力源材料填充源极和漏极凹陷来形成与栅极堆叠相关联的外延源极和漏极区域。

5. 发明申请

US20120187522A1 STRUCTURE AND METHOD FOR REDUCTION OF VT-W EFFECT IN HIGH-K METAL GATE DEVICES 审中-公开
标题翻译：用于降低高K金属栅极装置中VT-W效应的结构和方法
公开(公告)号：US20120187522A1
公开(公告)日：2012-07-26
申请号：US13010041
申请日：2011-01-20
申请人： Michael V. Aquilino , Christopher V. Baiocco , Richard A. Conti , Daniel J. Jaeger , Vijay Narayanan
发明人： Michael V. Aquilino , Christopher V. Baiocco , Richard A. Conti , Daniel J. Jaeger , Vijay Narayanan
IPC分类号： H01L29/06 , G06F17/50 , H01L21/762
CPC分类号： H01L29/0649 , H01L21/76229 , H01L29/517
摘要： A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices.
摘要翻译：提供基板。在衬底中形成STI沟槽。填充材料形成在STI沟槽中，然后平坦化。将衬底暴露于氧化环境中，在STI沟槽的底部和侧壁处生长衬垫。衬垫降低了高k金属栅极器件中的Vt-W效应。

6. 发明授权

US08053301B2 CMOS SiGe channel pFET and Si channel nFET devices with minimal STI recess 有权
标题翻译： CMOS SiGe沟道pFET和Si沟道nFET器件，具有最小的STI凹陷
公开(公告)号：US08053301B2
公开(公告)日：2011-11-08
申请号：US12413771
申请日：2009-03-30
申请人： Daniel J. Jaeger , Michael V. Aquilino , Christopher V. Baiocco
发明人： Daniel J. Jaeger , Michael V. Aquilino , Christopher V. Baiocco
IPC分类号： H01L21/8238 , H01L21/20
CPC分类号： H01L21/823878 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/66651
摘要： Silicon germanium (SiGe) is epitaxially grown on a silicon channel above nFET and pFET regions of a substrate. SiGe is removed above the nFET regions. A device includes a silicon channel above the nFET regions and a SiGe channel above the pFET regions.
摘要翻译：硅锗（SiGe）在衬底nFET和pFET区上的硅沟道上外延生长。在nFET区域之上去除SiGe。器件包括nFET区上方的硅沟道和pFET区上方的SiGe沟道。

7. 发明授权

US08969163B2 Forming facet-less epitaxy with self-aligned isolation 有权
标题翻译：用自对准隔离形成无面外延
公开(公告)号：US08969163B2
公开(公告)日：2015-03-03
申请号：US13556406
申请日：2012-07-24
申请人： Michael V. Aquilino , Byeong Yeol Kim , Ying Li , Carl John Radens
发明人： Michael V. Aquilino , Byeong Yeol Kim , Ying Li , Carl John Radens
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/70
CPC分类号： H01L21/76232 , H01L29/66628 , H01L29/66636
摘要： A method of forming a semiconductor structure may include preparing a continuous active layer in a region of the substrate and forming a plurality of adjacent gates on the continuous active layer. A first raised epitaxial layer may be deposited on a recessed region of the continuous active layer between a first and a second one of the plurality of gates, whereby the first and second gates are adjacent. A second raised epitaxial layer may be deposited on another recessed region of the continuous active layer between the second and a third one of the plurality of gates, whereby the second and third gates are adjacent. Using a cut mask, a trench structure is etched into the second gate structure and a region underneath the second gate in the continuous active layer. The trench is filled with isolation material for electrically isolating the first and second raised epitaxial layers.
摘要翻译：形成半导体结构的方法可以包括在衬底的区域中制备连续有源层，并在连续有源层上形成多个相邻栅极。第一凸起的外延层可以沉积在多个栅极中的第一和第二栅极之间的连续有源层的凹陷区域上，由此第一和第二栅极相邻。第二凸起的外延层可以沉积在多个栅极中的第二和第三栅极之间的连续有源层的另一个凹陷区域上，由此第二和第三栅极相邻。使用切割掩模，沟槽结构被蚀刻到第二栅极结构中以及连续有源层中的第二栅极下方的区域。沟槽填充有用于电隔离第一和第二凸起外延层的隔离材料。

8. 发明申请

US20140027820A1 FORMING FACET-LESS EPITAXY WITH SELF-ALIGNED ISOLATION 有权
标题翻译：具有自对准隔离的成形面较小的外观
公开(公告)号：US20140027820A1
公开(公告)日：2014-01-30
申请号：US13556406
申请日：2012-07-24
申请人： Michael V. Aquilino , Byeong Yeol Kim , Ying Li , Carl John Radens
发明人： Michael V. Aquilino , Byeong Yeol Kim , Ying Li , Carl John Radens
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/76232 , H01L29/66628 , H01L29/66636
摘要： A method of forming a semiconductor structure may include preparing a continuous active layer in a region of the substrate and forming a plurality of adjacent gates on the continuous active layer. A first raised epitaxial layer may be deposited on a recessed region of the continuous active layer between a first and a second one of the plurality of gates, whereby the first and second gates are adjacent. A second raised epitaxial layer may be deposited on another recessed region of the continuous active layer between the second and a third one of the plurality of gates, whereby the second and third gates are adjacent. Using a cut mask, a trench structure is etched into the second gate structure and a region underneath the second gate in the continuous active layer. The trench is filled with isolation material for electrically isolating the first and second raised epitaxial layers.
摘要翻译：形成半导体结构的方法可以包括在衬底的区域中制备连续有源层，并在连续有源层上形成多个相邻栅极。第一凸起的外延层可以沉积在多个栅极中的第一和第二栅极之间的连续有源层的凹陷区域上，由此第一和第二栅极相邻。第二凸起的外延层可以沉积在多个栅极中的第二和第三栅极之间的连续有源层的另一个凹陷区域上，由此第二和第三栅极相邻。使用切割掩模，沟槽结构被蚀刻到第二栅极结构中以及连续有源层中的第二栅极下方的区域。沟槽填充有用于电隔离第一和第二凸起外延层的隔离材料。

9. 发明授权

US08853796B2 High-K metal gate device 有权
标题翻译：高K金属门装置
公开(公告)号：US08853796B2
公开(公告)日：2014-10-07
申请号：US13110922
申请日：2011-05-19
申请人： Young Way Teh , Michael V. Aquilino , Arifuzzaman (Arif) Sheikh , Yun Ling Tan , Hao Zhang , Deleep R. Nair , Jinghong H. (John) Li
发明人： Young Way Teh , Michael V. Aquilino , Arifuzzaman (Arif) Sheikh , Yun Ling Tan , Hao Zhang , Deleep R. Nair , Jinghong H. (John) Li
IPC分类号： H01L29/772 , H01L21/28 , H01L29/423 , H01L29/51 , H01L29/49
CPC分类号： H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/518
摘要： A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.
摘要翻译：一种器件包括具有由隔离区域围绕的器件区域的衬底，其中器件区域包括沿着器件区域的宽度的边缘部分和中心部分。该器件还包括在器件区域上设置在衬底上的栅极层，其中栅极层包括梯度厚度，其中器件区域的边缘部分处的栅极层的厚度TE不同于设备区域的中心部分。

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