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1. 发明授权

US08859388B2 Sealed shallow trench isolation region 有权
标题翻译：密封浅沟槽隔离区
公开(公告)号：US08859388B2
公开(公告)日：2014-10-14
申请号：US13548237
申请日：2012-07-13
申请人： Michael V. Aquilino , Xiang Hu , Daniel J. Jaeger , Byeong Y. Kim , Yong M. Lee , Ying Li , Reinaldo A. Vega
发明人： Michael V. Aquilino , Xiang Hu , Daniel J. Jaeger , Byeong Y. Kim , Yong M. Lee , Ying Li , Reinaldo A. Vega
IPC分类号： H01L29/06 , H01L29/66 , H01L21/8234
CPC分类号： H01L21/823437 , H01L21/76224 , H01L29/66621
摘要： A method for formation of a sealed shallow trench isolation (STI) region for a semiconductor device includes forming a STI region in a substrate, the STI region comprising a STI fill; forming a sealing recess in the STI fill of the STI region; and forming a sealing layer in the sealing recess over the STI fill.
摘要翻译：用于形成用于半导体器件的密封浅沟槽隔离（STI）区域的方法包括在衬底中形成STI区域，所述STI区域包括STI填充物; 在STI区域的STI填充物中形成密封凹槽; 以及在所述STI填充物上的所述密封凹槽中形成密封层。

2. 发明申请

US20140015092A1 SEALED SHALLOW TRENCH ISOLATION REGION 有权
标题翻译：密封沙滩隔离区
公开(公告)号：US20140015092A1
公开(公告)日：2014-01-16
申请号：US13548237
申请日：2012-07-13
申请人： Michael V. Aquilino , Xiang Hu , Daniel J. Jaeger , Byeong Y. Kim , Yong M. Lee , Ying Li , Reinaldo A. Vega
发明人： Michael V. Aquilino , Xiang Hu , Daniel J. Jaeger , Byeong Y. Kim , Yong M. Lee , Ying Li , Reinaldo A. Vega
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/823437 , H01L21/76224 , H01L29/66621
摘要： A method for formation of a sealed shallow trench isolation (STI) region for a semiconductor device includes forming a STI region in a substrate, the STI region comprising a STI fill; forming a sealing recess in the STI fill of the STI region; and forming a sealing layer in the sealing recess over the STI fill.
摘要翻译：用于形成用于半导体器件的密封浅沟槽隔离（STI）区域的方法包括在衬底中形成STI区域，所述STI区域包括STI填充物; 在STI区域的STI填充物中形成密封凹槽; 以及在所述STI填充物上的所述密封凹槽中形成密封层。

3. 发明授权

US09035430B2 Semiconductor fin on local oxide 有权
标题翻译：半导体翅片局部氧化物
公开(公告)号：US09035430B2
公开(公告)日：2015-05-19
申请号：US13597799
申请日：2012-08-29
申请人： Reinaldo A. Vega , Michael V. Aquilino , Daniel J. Jaeger
发明人： Reinaldo A. Vega , Michael V. Aquilino , Daniel J. Jaeger
IPC分类号： H01L21/02 , H01L21/308 , H01L21/32 , H01L21/762 , H01L29/66 , H01L29/78
CPC分类号： H01L21/76281 , H01L21/3081 , H01L21/3086 , H01L21/32 , H01L21/76208 , H01L29/66795 , H01L29/785
摘要： A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins. The first semiconductor material can be selected from materials more easily oxidized relative to the second semiconductor material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer.
摘要翻译：提供了包括第一外延半导体层的半导体衬底。第一外延半导体层包括第一半导体材料，并且可以形成在下面的外延衬底层上，或者可以是整个半导体衬底。包含第二半导体材料的第二外延半导体层外延地形成在第一外延半导体层上。包括第二单晶半导体材料的部分的半导体翅片通过使用第一外延半导体层作为蚀刻停止层的第二外延半导体层图案化而形成。至少第一外延半导体层的上部被氧化以提供电绝缘半导体鳍片的局部氧化物层。第一半导体材料可以从相对于第二半导体材料更容易氧化的材料中选择，以在形成局部氧化物层之后为半导体翅片提供均匀的高度。

4. 发明申请

US20120187522A1 STRUCTURE AND METHOD FOR REDUCTION OF VT-W EFFECT IN HIGH-K METAL GATE DEVICES 审中-公开
标题翻译：用于降低高K金属栅极装置中VT-W效应的结构和方法
公开(公告)号：US20120187522A1
公开(公告)日：2012-07-26
申请号：US13010041
申请日：2011-01-20
申请人： Michael V. Aquilino , Christopher V. Baiocco , Richard A. Conti , Daniel J. Jaeger , Vijay Narayanan
发明人： Michael V. Aquilino , Christopher V. Baiocco , Richard A. Conti , Daniel J. Jaeger , Vijay Narayanan
IPC分类号： H01L29/06 , G06F17/50 , H01L21/762
CPC分类号： H01L29/0649 , H01L21/76229 , H01L29/517
摘要： A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices.
摘要翻译：提供基板。在衬底中形成STI沟槽。填充材料形成在STI沟槽中，然后平坦化。将衬底暴露于氧化环境中，在STI沟槽的底部和侧壁处生长衬垫。衬垫降低了高k金属栅极器件中的Vt-W效应。

5. 发明申请

US20100244198A1 CMOS SIGE CHANNEL PFET AND SI CHANNEL NFET DEVICES WITH MINIMAL STI RECESS 有权
标题翻译： CMOS信号通道PFET和SI通道NFET器件，具有最小的STI记录
公开(公告)号：US20100244198A1
公开(公告)日：2010-09-30
申请号：US12413771
申请日：2009-03-30
申请人： Daniel J. Jaeger , Michael ` V. Aquilino , Christopher V. Baiocco
发明人： Daniel J. Jaeger , Michael ` V. Aquilino , Christopher V. Baiocco
IPC分类号： H01L29/161 , H01L21/20
CPC分类号： H01L21/823878 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/66651
摘要： Silicon germanium (SiGe) is epitaxially grown on a silicon channel above nFET and pFET regions of a substrate. SiGe is removed above the nFET regions. A device includes a silicon channel above the nFET regions and a SiGe channel above the pFET regions.
摘要翻译：硅锗（SiGe）在衬底nFET和pFET区上的硅沟道上外延生长。在nFET区域之上去除SiGe。器件包括nFET区上方的硅沟道和pFET区上方的SiGe沟道。

6. 发明授权

US08053301B2 CMOS SiGe channel pFET and Si channel nFET devices with minimal STI recess 有权
标题翻译： CMOS SiGe沟道pFET和Si沟道nFET器件，具有最小的STI凹陷
公开(公告)号：US08053301B2
公开(公告)日：2011-11-08
申请号：US12413771
申请日：2009-03-30
申请人： Daniel J. Jaeger , Michael V. Aquilino , Christopher V. Baiocco
发明人： Daniel J. Jaeger , Michael V. Aquilino , Christopher V. Baiocco
IPC分类号： H01L21/8238 , H01L21/20
CPC分类号： H01L21/823878 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/66651
摘要： Silicon germanium (SiGe) is epitaxially grown on a silicon channel above nFET and pFET regions of a substrate. SiGe is removed above the nFET regions. A device includes a silicon channel above the nFET regions and a SiGe channel above the pFET regions.
摘要翻译：硅锗（SiGe）在衬底nFET和pFET区上的硅沟道上外延生长。在nFET区域之上去除SiGe。器件包括nFET区上方的硅沟道和pFET区上方的SiGe沟道。

7. 发明授权

US08569840B2 Bipolar transistor integrated with metal gate CMOS devices 失效
标题翻译：与金属栅极CMOS器件集成的双极晶体管
公开(公告)号：US08569840B2
公开(公告)日：2013-10-29
申请号：US13370523
申请日：2012-02-10
申请人： Thomas A. Wallner , Ebenezer E. Eshun , Daniel J. Jaeger , Phung T. Nguyen
发明人： Thomas A. Wallner , Ebenezer E. Eshun , Daniel J. Jaeger , Phung T. Nguyen
IPC分类号： H01L29/70 , H01L29/73 , H01L29/78
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.
摘要翻译：形成高k栅极电介质层和金属栅极层，并图案化以暴露双极结型晶体管区域中的半导体表面，同时覆盖CMOS区域。一次性材料部分形成在双极结型晶体管区域中暴露的半导体表面的一部分上。沉积半导体层和电介质层，以形成包括CMOS区域中的半导体部分和介电栅极盖的栅极堆叠，以及在双极结型晶体管区域中的一次性材料部分上的包含台面的空腔。选择性地去除一次性材料部分，并且包括外延部分和多晶部分的基层填充通过去除一次性材料部分而形成的空腔。通过选择性外延形成的发射体填充台面中的空腔。

8. 发明授权

US08129234B2 Method of forming bipolar transistor integrated with metal gate CMOS devices 失效
标题翻译：与金属栅极CMOS器件集成的双极晶体管的形成方法
公开(公告)号：US08129234B2
公开(公告)日：2012-03-06
申请号：US12556205
申请日：2009-09-09
申请人： Thomas A. Wallner , Ebenezer E. Eshun , Daniel J. Jaeger , Phung T. Nguyen
发明人： Thomas A. Wallner , Ebenezer E. Eshun , Daniel J. Jaeger , Phung T. Nguyen
IPC分类号： H01L21/8249
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.
摘要翻译：形成高k栅极电介质层和金属栅极层，并图案化以暴露双极结型晶体管区域中的半导体表面，同时覆盖CMOS区域。一次性材料部分形成在双极结型晶体管区域中暴露的半导体表面的一部分上。沉积半导体层和电介质层，以形成包括CMOS区域中的半导体部分和介电栅极盖的栅极堆叠，以及在双极结型晶体管区域中的一次性材料部分上的包含台面的空腔。选择性地去除一次性材料部分，并且包括外延部分和多晶部分的基层填充通过去除一次性材料部分而形成的空腔。通过选择性外延形成的发射体填充台面中的空腔。

9. 发明授权

US08704332B2 Metal oxide semiconductor field effect transistor (MOSFET) gate termination 有权
标题翻译：金属氧化物半导体场效应晶体管（MOSFET）门极端接
公开(公告)号：US08704332B2
公开(公告)日：2014-04-22
申请号：US13495081
申请日：2012-06-13
申请人： Christopher V. Baiocco , Daniel J. Jaeger , Carl J. Radens , Helen Wang
发明人： Christopher V. Baiocco , Daniel J. Jaeger , Carl J. Radens , Helen Wang
IPC分类号： H01L29/786 , H01L29/78 , H01L29/06
CPC分类号： H01L29/7816 , H01L21/28247 , H01L29/0642 , H01L29/0649 , H01L29/51 , H01L29/66477 , H01L29/66575 , H01L29/78
摘要： A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.
摘要翻译：提供一种形成半导体器件的方法，其包括在半导体衬底中形成含有隔离区的氧化物以限定有源半导体区域。然后可以在有源半导体区域上形成包括高k栅极电介质层的覆盖栅极堆叠。覆盖栅极堆叠的至少一部分从有源半导体器件区域延伸到隔离区域。然后可以对覆盖栅极堆叠进行蚀刻以在隔离区域上提供开口。然后可以对由开口暴露的隔离区域的表面进行各向同性蚀刻，以在隔离区域内形成在高k栅极电介质层下延伸的底切区域。然后可以在填充底切区域的开口中形成密封电介质材料。然后可以对覆盖栅极堆叠进行构图以形成栅极结构。

10. 发明申请

US20120139056A1 BIPOLAR TRANSISTOR INTEGRATED WITH METAL GATE CMOS DEVICES 失效
标题翻译：双极晶体管与金属栅CMOS集成器件集成
公开(公告)号：US20120139056A1
公开(公告)日：2012-06-07
申请号：US13370523
申请日：2012-02-10
申请人： Thomas A. Wallner , Ebenezer E. Eshun , Daniel J. Jaeger , Phung T. Nguyen
发明人： Thomas A. Wallner , Ebenezer E. Eshun , Daniel J. Jaeger , Phung T. Nguyen
IPC分类号： H01L27/06
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.
摘要翻译：形成高k栅极电介质层和金属栅极层，并图案化以暴露双极结型晶体管区域中的半导体表面，同时覆盖CMOS区域。一次性材料部分形成在双极结型晶体管区域中暴露的半导体表面的一部分上。沉积半导体层和电介质层，以形成包括CMOS区域中的半导体部分和介电栅极盖的栅极堆叠，以及在双极结型晶体管区域中的一次性材料部分上的包含台面的空腔。选择性地去除一次性材料部分，并且包括外延部分和多晶部分的基层填充通过去除一次性材料部分而形成的空腔。通过选择性外延形成的发射体填充台面中的空腔。

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