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1. 发明申请

US20130334618A1 METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) GATE TERMINATION 有权
标题翻译：金属氧化物半导体场效应晶体管（MOSFET）栅极终止
公开(公告)号：US20130334618A1
公开(公告)日：2013-12-19
申请号：US13495081
申请日：2012-06-13
申请人： Christopher V. Baiocco , Daniel J. Jaeger , Carl J. Radens , Helen Wang
发明人： Christopher V. Baiocco , Daniel J. Jaeger , Carl J. Radens , Helen Wang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L21/28247 , H01L29/0642 , H01L29/0649 , H01L29/51 , H01L29/66477 , H01L29/66575 , H01L29/78
摘要： A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.
摘要翻译：提供一种形成半导体器件的方法，其包括在半导体衬底中形成含有隔离区的氧化物以限定有源半导体区域。然后可以在有源半导体区域上形成包括高k栅极电介质层的覆盖栅极堆叠。覆盖栅极堆叠的至少一部分从有源半导体器件区域延伸到隔离区域。然后可以对覆盖栅极堆叠进行蚀刻以在隔离区域上提供开口。然后可以对由开口暴露的隔离区域的表面进行各向同性蚀刻，以在隔离区域内形成在高k栅极电介质层下延伸的底切区域。然后可以在填充底切区域的开口中形成密封电介质材料。然后可以对覆盖栅极堆叠进行构图以形成栅极结构。

2. 发明授权

US08704332B2 Metal oxide semiconductor field effect transistor (MOSFET) gate termination 有权
标题翻译：金属氧化物半导体场效应晶体管（MOSFET）门极端接
公开(公告)号：US08704332B2
公开(公告)日：2014-04-22
申请号：US13495081
申请日：2012-06-13
申请人： Christopher V. Baiocco , Daniel J. Jaeger , Carl J. Radens , Helen Wang
发明人： Christopher V. Baiocco , Daniel J. Jaeger , Carl J. Radens , Helen Wang
IPC分类号： H01L29/786 , H01L29/78 , H01L29/06
CPC分类号： H01L29/7816 , H01L21/28247 , H01L29/0642 , H01L29/0649 , H01L29/51 , H01L29/66477 , H01L29/66575 , H01L29/78
摘要： A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.
摘要翻译：提供一种形成半导体器件的方法，其包括在半导体衬底中形成含有隔离区的氧化物以限定有源半导体区域。然后可以在有源半导体区域上形成包括高k栅极电介质层的覆盖栅极堆叠。覆盖栅极堆叠的至少一部分从有源半导体器件区域延伸到隔离区域。然后可以对覆盖栅极堆叠进行蚀刻以在隔离区域上提供开口。然后可以对由开口暴露的隔离区域的表面进行各向同性蚀刻，以在隔离区域内形成在高k栅极电介质层下延伸的底切区域。然后可以在填充底切区域的开口中形成密封电介质材料。然后可以对覆盖栅极堆叠进行构图以形成栅极结构。

3. 发明申请

US20130032897A1 MOSFET GATE ELECTRODE EMPLOYING ARSENIC-DOPED SILICON-GERMANIUM ALLOY LAYER 审中-公开
标题翻译：使用砷化硅 - 锗合金层的MOSFET栅极电极
公开(公告)号：US20130032897A1
公开(公告)日：2013-02-07
申请号：US13196106
申请日：2011-08-02
申请人： Vijay Narayanan , Christopher V. Baiocco , Weipeng Li , Helen Wang
发明人： Vijay Narayanan , Christopher V. Baiocco , Weipeng Li , Helen Wang
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L21/26513 , H01L21/28088 , H01L21/28167 , H01L29/41783 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： A stack of a gate dielectric layer, a metallic material layer, an amorphous silicon-germanium alloy layer, and an amorphous silicon layer is deposited on a semiconductor substrate. In one embodiment, the amorphous silicon-germanium alloy layer is deposited as an in-situ amorphous arsenic-doped silicon-germanium alloy layer. In another embodiment, the amorphous silicon-germanium alloy layer is deposited as intrinsic semiconductor material layer, and arsenic is subsequently implanted into the amorphous silicon-germanium alloy layer. The stack is patterned and annealed to form a gate electrode.
摘要翻译：在半导体衬底上沉积有栅介电层，金属材料层，非晶硅 - 锗合金层和非晶硅层的叠层。在一个实施例中，非晶硅 - 锗合金层作为原位非晶砷掺杂硅 - 锗合金层沉积。在另一个实施例中，沉积非晶硅 - 锗合金层作为本征半导体材料层，随后将砷注入到非晶硅 - 锗合金层中。将叠层图案化并退火以形成栅电极。

4. 发明授权

US08507346B2 Method of forming a semiconductor device having a cut-way hole to expose a portion of a hardmask layer 有权
标题翻译：形成具有切割孔以暴露硬掩模层的一部分的半导体器件的方法
公开(公告)号：US08507346B2
公开(公告)日：2013-08-13
申请号：US12949148
申请日：2010-11-18
申请人： Martin Burkhardt , Matthew E. Colburn , Allen H. Gabor , Oleg Gluschenkov , Scott D. Halle , Howard S. Landis , Helen Wang
发明人： Martin Burkhardt , Matthew E. Colburn , Allen H. Gabor , Oleg Gluschenkov , Scott D. Halle , Howard S. Landis , Helen Wang
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/84 , H01L21/338 , H01L21/3205 , H01L21/4763 , H01L21/311 , H01L21/302 , H01L21/461
CPC分类号： H01L29/78 , H01L21/28123 , H01L21/32139 , H01L22/12 , H01L22/26
摘要： A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.
摘要翻译：一种形成具有衬底，有源区和非活性区的半导体器件的方法包括：在衬底上形成硬掩模层; 将第一图案转移到半导体器件的有源区中的硬掩模层中; 在非活性区域中形成一个或多个填充物; 在所述一个或多个填充物内部，覆盖或部分地覆盖所述硬掩模层的一部分以暴露所述硬掩模层的一部分内的切除孔，所述暴露部分在所述一个或多个填充物内; 以及将所述硬掩模层暴露于蚀刻剂以将所述第一图案划分成包括至少两个分离元件的第二图案。

5. 发明申请

US20090181330A1 METHODS FOR FORMING A COMPOSITE PATTERN INCLUDING PRINTED RESOLUTION ASSIST FEATURES 有权
标题翻译：用于形成复合图案的方法，包括印刷分辨率辅助特征
公开(公告)号：US20090181330A1
公开(公告)日：2009-07-16
申请号：US12013627
申请日：2008-01-14
申请人： Allen H. Gabor , Scott D. Halle , Helen Wang
发明人： Allen H. Gabor , Scott D. Halle , Helen Wang
IPC分类号： G03F7/20
CPC分类号： H01L21/0337 , G03F7/70433 , G03F7/70466
摘要： An underlayer to be patterned with a composite pattern is formed on a substrate. The composite pattern is decomposed into a first pattern and a second pattern, each having reduced complexity than the composite pattern. A hard mask layer is formed directly on the underlying layer. A first photoresist is applied over the hard mask layer and lithographically patterned with the first pattern, which is transferred into the hard mask layer by a first etch. A second photoresist is applied over the hard mask layer. The second photoresist is patterned with the second pattern to expose portions of the underlying layer. The exposed portions of the underlying layer are etched employing the second photoresist and the hard mask layer, which contains the first pattern so that the composite pattern is transferred into the underlying layer.
摘要翻译：在基板上形成图案化复合图案的底层。复合图案被分解为第一图案和第二图案，每个图案具有比复合图案更低的复杂度。硬掩模层直接形成在下层上。将第一光致抗蚀剂施加在硬掩模层上并用第一图案进行光刻图案化，其通过第一蚀刻转移到硬掩模层中。在硬掩模层上施加第二光致抗蚀剂。用第二图案对第二光致抗蚀剂进行图案化以暴露下层的部分。使用包含第一图案的第二光致抗蚀剂和硬掩模层来蚀刻下层的暴露部分，使得复合图案被转移到下层中。

6. 发明申请

US20080286698A1 Semiconductor device manufacturing methods 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：US20080286698A1
公开(公告)日：2008-11-20
申请号：US11804528
申请日：2007-05-18
申请人： Haoren Zhuang , Chong Kwang Chang , Alois Gutmann , Jingyu Lian , Matthias Lipinski , Len Yuan Tsou , Helen Wang
发明人： Haoren Zhuang , Chong Kwang Chang , Alois Gutmann , Jingyu Lian , Matthias Lipinski , Len Yuan Tsou , Helen Wang
IPC分类号： H01L21/02 , G03C5/00
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/84
摘要： Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. An additional substance is introduced and the lower portion of the masking material is patterned. The masking material and the additional substance are used to pattern the material layer of the workpiece.
摘要翻译：公开了制造半导体器件的方法。一个优选实施例是一种处理半导体器件的方法。该方法包括提供具有设置在其上的待图案化材料层的工件。在工件的材料层上形成掩模材料。掩模材料包括下部和设置在下部上的上部。用第一图案对掩模材料的上部进行图案化。引入另外的物质，掩模材料的下部被图案化。掩模材料和附加物质用于对工件的材料层进行图案化。

7. 发明申请

US20080244712A1 SYSTEM AND METHOD FOR AUTHENTICATING A USER OF AN IMAGE PROCESSING SYSTEM 失效
标题翻译：用于认证图像处理系统的用户的系统和方法
公开(公告)号：US20080244712A1
公开(公告)日：2008-10-02
申请号：US11692957
申请日：2007-03-29
申请人： Hiroshi KITADA , Lana Wong , Helen Wang , Weiyun Tang , Andrew Jennings , Revathi Vellanki
发明人： Hiroshi KITADA , Lana Wong , Helen Wang , Weiyun Tang , Andrew Jennings , Revathi Vellanki
IPC分类号： G06F7/04
CPC分类号： G06F21/41 , G06F21/82
摘要： A system and method for authenticating a user of an image processing system. User credentials are received at an authentication device corresponding to an image processing device, and transmitted to a first server remote from the authentication device. The validity of the user credentials are judged by comparing the received user credentials to authentication information stored at the first server, and a result of the judging is transmitted to the image processing device. The image processing device then requests access to a second server remote from the image processing device, and the second server transmits a request for the user credentials to the first server. After receiving the user credentials from the first server, the second server performs user authentication.
摘要翻译：一种用于认证图像处理系统的用户的系统和方法。在与图像处理设备相对应的认证设备处接收用户凭证，并将其发送到远离认证设备的第一服务器。通过将接收到的用户凭证与存储在第一服务器上的认证信息进行比较来判断用户凭证的有效性，并将判断结果发送给图像处理装置。然后，图像处理设备请求访问远离图像处理设备的第二服务器，并且第二服务器向第一服务器发送用于用户凭证的请求。在从第一服务器接收到用户凭证之后，第二服务器执行用户认证。

8. 发明授权

US07426677B2 Layered multiple description coding 有权
标题翻译：分层多重描述编码
公开(公告)号：US07426677B2
公开(公告)日：2008-09-16
申请号：US11787387
申请日：2007-04-16
申请人： Philip Andrew Chou , Venkata N. Padmanabhan , Helen Wang
发明人： Philip Andrew Chou , Venkata N. Padmanabhan , Helen Wang
IPC分类号： H03M13/00
CPC分类号： H04N21/6405 , H04N19/39
摘要： A data sequence may be encoded in a plurality of layers of multiple description coding. The layers of multiple description coding may include a first and a second layer of multiple description coding. The first layer of multiple description coding may include an initial part of a data sequence as well as forward error correction code for the initial part. The second layer of multiple description coding may include a next part of the data sequence as well as forward error correction code for the next part. A first set of data sequence breakpoints may be determined for the first layer of multiple description coding. A second set of data sequence breakpoints may be determined for the second layer. The data sequence may be encoded in the plurality of layers of multiple description coding as a function of the first and second sets of data sequence breakpoints.
摘要翻译：数据序列可以被编码在多个多描述编码层中。多描述编码的层可以包括多描述编码的第一和第二层。多描述编码的第一层可以包括数据序列的初始部分以及初始部分的前向纠错码。多重描述编码的第二层可以包括数据序列的下一部分以及下一部分的前向纠错码。可以为第一层多重描述编码确定第一组数据序列断点。可以为第二层确定第二组数据序列断点。数据序列可以在多个描述编码的多个层中作为第一和第二组数据序列断点进行编码。

9. 发明申请

US20050132438A1 Novel monocotylednous plant genes and uses thereof 审中-公开
标题翻译：新型单子叶植物基因及其用途
公开(公告)号：US20050132438A1
公开(公告)日：2005-06-16
申请号：US10220665
申请日：2001-03-05
申请人： Helen Wang , John Salmeron , Michael Willits , Kay Lawton
发明人： Helen Wang , John Salmeron , Michael Willits , Kay Lawton
IPC分类号： A01H5/00 , C07K14/415 , C12N1/15 , C12N1/19 , C12N1/21 , C12N5/10 , C12N15/09 , C12N15/29 , C12N15/82 , C12Q1/68 , A01H1/00 , C07H21/04 , C12N5/04 , C12N9/24
CPC分类号： C12N15/8279 , C07K14/415
摘要： Homologues of the Arabidopsis NIM1 gene, which is involved in the signal transduction cascade leading to systemic acquired resistance (SAR), are isolated from monocotyledonous crops such as Triticum aestivum (wheat) and Oryza sativa (rice). The invention further concerns transformation vectors and processes for expressing the monocotyledonous NIM1 homologues in transgenic plants to increase SAR gene expression and enhance broad spectrum disease resistance
摘要翻译：拟南芥NIM1基因的同源物，其参与导致系统性获得性抗性（SAR）的信号转导级联，从单子叶作物如小麦（Triticum aestivum）（小麦）和水稻（Rice）中分离。本发明还涉及用于在转基因植物中表达单子叶NIM1同源物的转化载体和方法，以增加SAR基因表达并增强广谱抗病性

10. 发明授权

US07550303B2 Systems and methods for overlay shift determination 失效
标题翻译：覆盖变换确定的系统和方法
公开(公告)号：US07550303B2
公开(公告)日：2009-06-23
申请号：US11279534
申请日：2006-04-12
申请人： Patricia Argandona , Faisal Azam , Andrew Lu , Helen Wang
发明人： Patricia Argandona , Faisal Azam , Andrew Lu , Helen Wang
IPC分类号： H01L21/66 , G06F19/00
CPC分类号： H01L22/34
摘要： Method for measuring misalignment between at least two layers of an integrated circuit. The method includes applying a current between a plurality of probe members in a first layer, wherein a first probe member and a second probe member of the plurality of probe members are substantially aligned along a first axis and partially overlap an overlay target in a second layer, measuring a voltage across the plurality of probe members wherein at least a voltage across the first probe member and a third probe member disposed perpendicular to the first axis and a voltage across the second probe member and the third probe member are measured, and determining an amount of misalignment between the first layer and the second layer along at least one of the first axis and the second axis based on the measuring steps.
摘要翻译：用于测量集成电路的至少两层之间的未对准的方法。该方法包括在第一层中的多个探针构件之间施加电流，其中多个探针构件中的第一探针构件和第二探针构件沿着第一轴线基本上对准并且部分地与第二层中的覆盖目标重叠测量所述多个探针构件上的电压，其中测量所述第一探针构件和垂直于所述第一轴线设置的至少一个电压以及横跨所述第二探针构件和所述第三探针构件的电压，并且确定基于测量步骤沿着第一轴和第二轴的至少一个，第一层和第二层之间的未对准量。

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