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1. 发明授权

US07725556B1 Computer system with concurrent direct memory access 有权
标题翻译：具有并发直接内存访问的计算机系统
公开(公告)号：US07725556B1
公开(公告)日：2010-05-25
申请号：US11553953
申请日：2006-10-27
申请人： Michael S. Schlansker , Erwin Oertli , Norm Jouppi
发明人： Michael S. Schlansker , Erwin Oertli , Norm Jouppi
IPC分类号： G06F15/167 , G06F15/173 , G06F3/00 , G06F13/00
CPC分类号： G06F13/28 , G06F13/385
摘要： A computer system with concurrent direct memory access is provided including a computer node having a processor interface bus and a cut-through network interface controller installed on the processor interface bus. A data transfer is initiated through the cut-through network interface controller by starting a direct memory access to move data from a memory to a transmit buffer in the cut-through network interface controller and a network interface controller physical interface transmitting the data, to the computer node attached to a reliable network, before all of the data is in the transmit buffer.
摘要翻译：提供具有并发直接存储器访问的计算机系统，包括具有处理器接口总线的计算机节点和安装在处理器接口总线上的直通式网络接口控制器。通过直通网络接口控制器启动数据传输，通过启动直接存储器访问来将数据从直通网络接口控制器中的存储器移动到发送缓冲器，以及将数据传输到网络接口控制器物理接口计算机节点附加到可靠的网络，所有的数据都在发送缓冲区中。

2. 发明授权

US08909872B1 Computer system with coherent interconnection 有权
标题翻译：具有相干互连的计算机系统
公开(公告)号：US08909872B1
公开(公告)日：2014-12-09
申请号：US11555215
申请日：2006-10-31
申请人： Michael S. Schlansker , Boon Ang , Erwin Oertli
发明人： Michael S. Schlansker , Boon Ang , Erwin Oertli
IPC分类号： G06F12/00
CPC分类号： G06F12/0835 , G06F2212/1016
摘要： A computer system is provided including a central processing unit having an internal cache, a memory controller is coupled to the central processing unit, and a closely coupled peripheral is coupled to the central processing unit. A coherent interconnection may exist between the internal cache and both the memory controller and the closely coupled peripheral, wherein the coherent interconnection is a bus.
摘要翻译：提供了包括具有内部高速缓存的中央处理单元的计算机系统，存储器控制器耦合到中央处理单元，并且紧密耦合的外围设备耦合到中央处理单元。内部高速缓存与存储器控制器和紧密耦合的外围设备之间可能存在相干互连，其中相干互连是总线。

3. 发明授权

US08683000B1 Virtual network interface system with memory management 有权
标题翻译：具有内存管理的虚拟网络接口系统
公开(公告)号：US08683000B1
公开(公告)日：2014-03-25
申请号：US11553976
申请日：2006-10-27
申请人： Michael S. Schlansker , Erwin Oertli
发明人： Michael S. Schlansker , Erwin Oertli
IPC分类号： G06F15/16
CPC分类号： H04L47/39
摘要： A virtual network interface system with memory management is provided, including a network interface controller having a memory with a memory credit and a flow-control for managing the network interface controller. A computer cluster is linked to the network interface controller for exchanging the memory credit with the network interface controller.
摘要翻译：提供具有存储器管理的虚拟网络接口系统，包括具有存储器存储器的网络接口控制器和用于管理网络接口控制器的流量控制。计算机集群被链接到网络接口控制器以与网络接口控制器交换存储信用。

4. 发明授权

US07788437B2 Computer system with network interface retransmit 有权
标题翻译：具有网络接口重传的计算机系统
公开(公告)号：US07788437B2
公开(公告)日：2010-08-31
申请号：US11553970
申请日：2006-10-27
申请人： Michael S. Schlansker , Boon Ang , Erwin Oertli
发明人： Michael S. Schlansker , Boon Ang , Erwin Oertli
IPC分类号： G06F13/14 , G06F13/00
CPC分类号： G06F13/385 , H04L49/90 , H04L49/9063
摘要： A computer system is provided including a computer having a bus coupled to a computer system memory with a user buffer allocated therein. A network interface controller is coupled between the bus and a network. A retransmit buffer is coupled to the computer system memory, a transmit/receive buffer coupled to the computer system memory, and a retransmit direct memory access is within the network interface controller for moving data between the user buffer and the transmit/receive buffer, the retransmit buffer, or both as well as for moving the data to the network.
摘要翻译：提供了一种计算机系统，包括计算机，该计算机具有耦合到其中分配有用户缓冲器的计算机系统存储器的总线。网络接口控制器耦合在总线和网络之间。重发缓冲器耦合到计算机系统存储器，耦合到计算机系统存储器的发送/接收缓冲器，并且重新发送直接存储器访问在网络接口控制器内，用于在用户缓冲器和发送/接收缓冲器之间移动数据，重传缓冲区，或两者以及将数据移动到网络。

5. 发明申请

US20080162663A1 COMPUTER SYSTEM WITH NETWORK INTERFACE RETRANSMIT 有权
标题翻译：具有网络接口重新计算的计算机系统
公开(公告)号：US20080162663A1
公开(公告)日：2008-07-03
申请号：US11553970
申请日：2006-10-27
申请人： Michael S. Schlansker , Boon Ang , Erwin Oertli
发明人： Michael S. Schlansker , Boon Ang , Erwin Oertli
IPC分类号： G06F15/16
CPC分类号： G06F13/385 , H04L49/90 , H04L49/9063
摘要： A computer system is provided including a computer having a bus coupled to a computer system memory with a user buffer allocated therein. A network interface controller is coupled between the bus and a network. A retransmit buffer is coupled to the computer system memory, a transmit/receive buffer coupled to the computer system memory, and a retransmit direct memory access is within the network interface controller for moving data between the user buffer and the transmit/receive buffer, the retransmit buffer, or both as well as for moving the data to the network.
摘要翻译：提供了一种计算机系统，包括计算机，该计算机具有耦合到其中分配有用户缓冲器的计算机系统存储器的总线。网络接口控制器耦合在总线和网络之间。重发缓冲器耦合到计算机系统存储器，耦合到计算机系统存储器的发送/接收缓冲器，并且重新发送直接存储器访问在网络接口控制器内，用于在用户缓冲器和发送/接收缓冲器之间移动数据，重传缓冲区，或两者以及将数据移动到网络。

6. 发明授权

US07975068B2 System and method for self configuration of reconfigurable systems 有权
公开(公告)号：US07975068B2
公开(公告)日：2011-07-05
申请号：US11540480
申请日：2006-09-28
申请人： Michael S. Schlansker , Boon Seong Ang , Philip J. Kuekes
发明人： Michael S. Schlansker , Boon Seong Ang , Philip J. Kuekes
IPC分类号： G06F15/173
CPC分类号： G06F15/7867
摘要： The invention is a system and method for reconfigurable computers. The invention involves a plurality of reconfigurable component clusters (RCCs), each of which can change their respective configuration upon receiving a configuration command. The invention uses a reconfiguration network for distributing the configuration command to the RCCs, wherein the reconfiguration network comprises a plurality of cells, wherein each RCC is connected to a cell.

7. 发明授权

US5615386A Computer architecture for reducing delays due to branch instructions 失效
标题翻译：用于减少分支指令导致的延迟的计算机体系结构
公开(公告)号：US5615386A
公开(公告)日：1997-03-25
申请号：US588151
申请日：1996-01-18
申请人： Frederic C. Amerson , Rajiv Gupta , Balasubramanian Kumar , Michael S. Schlansker , William S. Worley
发明人： Frederic C. Amerson , Rajiv Gupta , Balasubramanian Kumar , Michael S. Schlansker , William S. Worley
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/3844
摘要： An improved data processing system for executing branch instructions which has lower latency times and which only rarely requires the instruction pipeline to be flushed is disclosed. The data processing system utilizes a register file to hold the information needed to execute a branch instruction. The information is loaded into the register file in advance of the branch instruction. This allows the system to prepare more than one branch instruction at any given time. The present invention may be used to cause the cache line containing the target address of the branch instruction to be loaded soon as the target address is available for the branch instruction. Since the outcome of the branch instruction is almost always known when the branch instruction enters the instruction pipeline, the instruction pipeline only rarely needs to be flushed.
摘要翻译：公开了一种用于执行具有较低等待时间并且很少需要刷新指令流水线的分支指令的改进的数据处理系统。数据处理系统利用寄存器文件来保存执行分支指令所需的信息。信息在分支指令之前被加载到寄存器文件中。这允许系统在任何给定时间准备多个分支指令。本发明可以用于使得包含分支指令的目标地址的高速缓存线在目标地址对于分支指令可用时很快被加载。由于分支指令的结果在分支指令进入指令流水线时几乎总是被知道，所以指令流水线很少需要刷新。

8. 发明授权

US08452867B2 Systems and methods for network and server power management 有权
标题翻译：网络和服务器电源管理的系统和方法
公开(公告)号：US08452867B2
公开(公告)日：2013-05-28
申请号：US12848664
申请日：2010-08-02
申请人： Priya Mahadevan , Yoshio F. Turner , Michael S. Schlansker
发明人： Priya Mahadevan , Yoshio F. Turner , Michael S. Schlansker
IPC分类号： G06F15/173
CPC分类号： G06F1/3203 , G06F9/5094 , Y02D10/22
摘要： The present disclosure includes a system and method for managing network and server power. In an example of managing network and server power according to the present disclosure, routing network traffic is routed onto a number of core networks based on core network statistics, capacity requirements are determined based on core network statistics for the number of core networks and for a number of servers operating a number of virtual machines on the number of core networks, wherein the number of core networks include a number of core switches and a number of edge switches, and the capacity is set for the number of core switches based on the capacity requirements for the number of core networks and for the number of servers based on the capacity requirements for the number of servers.
摘要翻译：本公开包括用于管理网络和服务器功率的系统和方法。在根据本公开的管理网络和服务器电力的示例中，基于核心网络统计信息将路由网络业务路由到多个核心网络，基于核心网络的核心网络统计确定容量要求，并且对于核心网络数量的多个虚拟机的服务器数量，其中核心网络的数量包括多个核心交换机和多个边缘交换机，并且基于容量为核心交换机的数量设置容量基于服务器数量的容量要求，核心网络数量和服务器数量的要求。

9. 发明授权

US07146480B2 Configurable memory system 失效
标题翻译：可配置内存系统
公开(公告)号：US07146480B2
公开(公告)日：2006-12-05
申请号：US10350458
申请日：2003-01-23
申请人： Michael S. Schlansker , Boon Seong Ang
发明人： Michael S. Schlansker , Boon Seong Ang
IPC分类号： G06F12/00 , G06F13/00 , G06F13/14 , G06F15/00 , H04L7/00
CPC分类号： G06F13/1652
摘要： A configurable memory system is disclosed, which includes a processor-to-memory network, a memory-to-processor network, and a plurality of memory modules. Both networks in turns include a plurality of transport cells that can be configured to implement various transport networks, one for a particular memory application. To implement different memory applications in the same configurable memory system, a system designer takes several steps. The system designer identifies memory applications to be implemented in the configurable memory system. For each memory application, the designer allocates a set of memory modules and a transport network carrying data for the memory modules. Each transport network corresponding to a memory application thus establishes the data paths to and from the memory modules for that memory application. For each transport cell in the allocated networks, the designer develops a configuration table indicating the transport networks, one being associated with a memory application using that transport cell. The designer then creates reservation and/or conflict tables describing the timing relationships between the memory applications. Based on the reservation and/or conflict tables, scheduling execution of the memory applications can be performed.
摘要翻译：公开了一种可配置的存储器系统，其包括处理器到存储器网络，存储器到处理器网络和多个存储器模块。两个网络依次包括可被配置为实现各种传输网络的多个传输小区，一个用于特定的存储器应用。为了在同一可配置的存储器系统中实现不同的存储器应用，系统设计者需要几个步骤。系统设计者识别要在可配置存储器系统中实现的存储器应用。对于每个存储器应用，设计者分配一组存储器模块和传送网络，以携带用于存储器模块的数据。因此，对应于存储器应用的每个传输网络建立到该存储器应用的存储器模块的数据路径。对于分配的网络中的每个传输小区，设计者开发指示传输网络的配置表，一个与使用该传输小区的存储器应用相关联。然后，设计者创建描述存储器应用之间的时序关系的预留和/或冲突表。基于预留和/或冲突表，可以执行存储器应用的调度执行。

10. 发明授权

US06457173B1 Automatic design of VLIW instruction formats 失效
标题翻译：自动设计VLIW指令格式
公开(公告)号：US06457173B1
公开(公告)日：2002-09-24
申请号：US09378293
申请日：1999-08-20
申请人： Shail Aditya Gupta , B. Ramakrishna Rau , Richard C. Johnson , Michael S. Schlansker
发明人： Shail Aditya Gupta , B. Ramakrishna Rau , Richard C. Johnson , Michael S. Schlansker
IPC分类号： G06F945
CPC分类号： G06F9/30156 , G06F9/30167 , G06F9/3822 , G06F17/5045
摘要： A computer-implemented method automates the design of efficient binary instruction encodings of VLIW instruction formats. The method automatically finds compact instruction formats that can express and exploit the full parallelism specified in the underlying processor microarchitecture, subject to constraints on alignment and decode hardware complexity. The method can be guided by statistics about the composition and frequency of program instructions, so that the instruction format design is customized to a particular set of applications or an application domain.
摘要翻译：计算机实现的方法自动设计VLIW指令格式的有效二进制指令编码。该方法自动发现紧凑的指令格式，可以表达和利用底层处理器微体系结构中指定的完全并行性，受限于对齐和解码硬件复杂性。该方法可以通过关于程序指令的组成和频率的统计来指导，使得指令格式设计被定制成特定的一组应用或应用领域。

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