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1. 发明授权

US06457173B1 Automatic design of VLIW instruction formats 失效
标题翻译：自动设计VLIW指令格式
公开(公告)号：US06457173B1
公开(公告)日：2002-09-24
申请号：US09378293
申请日：1999-08-20
申请人： Shail Aditya Gupta , B. Ramakrishna Rau , Richard C. Johnson , Michael S. Schlansker
发明人： Shail Aditya Gupta , B. Ramakrishna Rau , Richard C. Johnson , Michael S. Schlansker
IPC分类号： G06F945
CPC分类号： G06F9/30156 , G06F9/30167 , G06F9/3822 , G06F17/5045
摘要： A computer-implemented method automates the design of efficient binary instruction encodings of VLIW instruction formats. The method automatically finds compact instruction formats that can express and exploit the full parallelism specified in the underlying processor microarchitecture, subject to constraints on alignment and decode hardware complexity. The method can be guided by statistics about the composition and frequency of program instructions, so that the instruction format design is customized to a particular set of applications or an application domain.
摘要翻译：计算机实现的方法自动设计VLIW指令格式的有效二进制指令编码。该方法自动发现紧凑的指令格式，可以表达和利用底层处理器微体系结构中指定的完全并行性，受限于对齐和解码硬件复杂性。该方法可以通过关于程序指令的组成和频率的统计来指导，使得指令格式设计被定制成特定的一组应用或应用领域。

2. 发明授权

US06651222B2 Automatic design of VLIW processors 失效
公开(公告)号：US06651222B2
公开(公告)日：2003-11-18
申请号：US10068216
申请日：2002-02-06
申请人： Shail Aditya Gupta , B. Ramakrishna Rau , Vinod K. Kathail , Michael S. Schlansker
发明人： Shail Aditya Gupta , B. Ramakrishna Rau , Vinod K. Kathail , Michael S. Schlansker
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F2217/68
摘要： A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.

3. 发明授权

US06385757B1 Auto design of VLIW processors 失效
标题翻译： VLIW处理器的自动设计
公开(公告)号：US06385757B1
公开(公告)日：2002-05-07
申请号：US09378395
申请日：1999-08-20
申请人： Shail Aditya Gupta , B. Ramakrishna Rau , Vinod K. Kathail , Michael S. Schlansker
发明人： Shail Aditya Gupta , B. Ramakrishna Rau , Vinod K. Kathail , Michael S. Schlansker
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F2217/68
摘要： A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.
摘要翻译： VLIW处理器设计系统可自动设计可编程和不可编程的VLIW处理器。系统将输入操作码，操作码的I / O格式，寄存器文件规范以及指令级并行约束作为输入。通过该输入规范，系统从宏单元数据库构建数据通路，包括功能单元，寄存器文件及其互连组件。系统使用输入和数据路径生成指令格式设计。然后可以使用指令格式来构造处理器控制路径。抽象输入和数据路径可以用于提取适合于将编译器重新定位到处理器的机器描述。为了优化特定应用程序的处理器，系统根据由重定向编译器生成的应用程序的操作问题统计信息选择自定义指令模板。

4. 发明授权

US06581187B2 Automatic design of VLIW processors 失效
公开(公告)号：US06581187B2
公开(公告)日：2003-06-17
申请号：US10068723
申请日：2002-02-06
申请人： Shail Aditya Gupta , B. Ramakrishna Rau , Vinod K. Kathail , Michael S. Schlansker
发明人： Shail Aditya Gupta , B. Ramakrishna Rau , Vinod K. Kathail , Michael S. Schlansker
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F2217/68
摘要： A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.

5. 发明授权

US06853970B1 Automatic design of processor datapaths 失效
标题翻译：自动设计处理器数据路径
公开(公告)号：US06853970B1
公开(公告)日：2005-02-08
申请号：US09378596
申请日：1999-08-20
申请人： Shail Aditya Gupta , B. Ramakrishna Rau
发明人： Shail Aditya Gupta , B. Ramakrishna Rau
IPC分类号： G06F9/44 , G06F13/10 , G06F13/12 , G06F17/50
CPC分类号： G06F17/5045
摘要： A method for the automatic design of processor datapaths operates on an abstract input specification of desired processor operations and their instruction level parallelism and synthesizes a datapath design in machine readable form. A datapath synthesizer automatically designs and synthesizes the processor datapath including the number and types of functional units, the number of read/write ports of the various register files, and the exact connectivity between the register files and the functional units. The heuristics used in the implementation maximize resource sharing and minimize the overall cost in by customizing and sharing functional units and minimizing the number of read/write ports on the register files subject to the specified ILP among operations.
摘要翻译：一种用于自动设计处理器数据路径的方法是在所需处理器操作的抽象输入规范及其指令级并行性的基础上进行操作，并以机器可读形式合成数据路径设计。数据路径合成器自动设计和合成处理器数据路径，包括功能单元的数量和类型，各种寄存器文件的读/写端口数，以及寄存器文件和功能单元之间的确切连接。实现中使用的启发式方法最大化资源共享，并通过定制和共享功能单元并最大限度地减少受操作中指定ILP的寄存器文件的读/写端口数量，从而最大限度地降低总体成本。

6. 发明授权

US06507947B1 Programmatic synthesis of processor element arrays 失效
标题翻译：处理器元件阵列的程序化合成
公开(公告)号：US06507947B1
公开(公告)日：2003-01-14
申请号：US09378298
申请日：1999-08-20
申请人： Robert S. Schreiber , B. Ramakrishna Rau , Shail Aditya Gupta , Vinod K. Kathail , Sadun Anik
发明人： Robert S. Schreiber , B. Ramakrishna Rau , Shail Aditya Gupta , Vinod K. Kathail , Sadun Anik
IPC分类号： G06F945
CPC分类号： G06F8/452 , G06F17/5045
摘要： A programmatic method transforms a nested loop in a high level programming language into a set of parallel processes, each a single time loop, such that the parallel processes satisfy a specified design constraint. Another programmatic method synthesizes a processor array from the set of parallel processes and a specified design constraint.
摘要翻译：一种编程方法将高级编程语言中的嵌套循环转换为一组并行进程，每个进程都是单个时间循环，以使并行进程满足指定的设计约束。另一个编程方法从并行进程集合和指定的设计约束合成处理器阵列。

7. 发明授权

US06490716B1 Automated design of processor instruction units 失效
标题翻译：处理器指令单元的自动设计
公开(公告)号：US06490716B1
公开(公告)日：2002-12-03
申请号：US09378394
申请日：1999-08-20
申请人： Shail Aditya Gupta , B. Ramakrishna Rau
发明人： Shail Aditya Gupta , B. Ramakrishna Rau
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： An automated method for designing a processor's control path employs program routines that synthesize the control path based on the processor's instruction format and data path specification. It extracts parameters from a machine-readable description of the processor's instruction format, and generates a specification of the components in the control path and their interconnection with the control ports in the data path.
摘要翻译：用于设计处理器的控制路径的自动化方法采用基于处理器的指令格式和数据路径规范来合成控制路径的程序例程。它从处理器指令格式的机器可读描述中提取参数，并且生成控制路径中的组件的规范及其与数据路径中的控制端口的互连。

8. 发明授权

US5778219A Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations 失效
标题翻译：在数据寄存器中传播异常状态的方法和系统，以及用非投机操作检测投机操作的异常
公开(公告)号：US5778219A
公开(公告)日：1998-07-07
申请号：US597784
申请日：1996-02-07
申请人： Frederic C. Amerson , Rajiv Gupta , Vinod K. Kathail , B. Ramakrishna Rau , Michael S. Schlansker , William S. Worley, Jr.
发明人： Frederic C. Amerson , Rajiv Gupta , Vinod K. Kathail , B. Ramakrishna Rau , Michael S. Schlansker , William S. Worley, Jr.
IPC分类号： G06F9/318 , G06F9/38
CPC分类号： G06F9/3865 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3863
摘要： A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file. If an exception is detected, then the exception is processed and one or more of the speculative operation are re-executed (in a non-speculative mode) where necessary to process the exception.
摘要翻译：支持投机执行的方法包括将操作指定为投机或非投机性，然后推迟由投机操作产生的异常，同时立即通过非投机操作报告异常。如果推测操作使用产生异常的推测操作的结果，则会传播该异常。使用检查操作检测和报告延期异常，并将其合并到非推测操作中或作为单独检查操作插入。用于支持推测执行的系统包括用于识别投机操作并推迟由这种操作产生的任何异常的功能单元。功能单元可以通过存储指示在寄存器文件中发生错误的信息来延迟异常。要检查延迟异常，功能单元然后读取寄存器文件。如果检测到异常，则处理异常，并且在需要处理异常的情况下重新执行一个或多个推测操作（以非推测模式）。

9. 发明授权

US5710912A Method and apparatus for enabling a computer system to adjust for latency assumptions 失效
标题翻译：使计算机系统能够调整等待时间假设的方法和装置
公开(公告)号：US5710912A
公开(公告)日：1998-01-20
申请号：US059041
申请日：1993-05-06
申请人： Michael S. Schlansker , B. Ramakrishna Rau , Rajiv Gupta , Joseph A. Fisher
发明人： Michael S. Schlansker , B. Ramakrishna Rau , Rajiv Gupta , Joseph A. Fisher
IPC分类号： G06F9/38 , G06F15/16
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3869
摘要： A method and system are disclosed which allow a computer program to execute properly in object code compatible processing systems which have latencies different from those with which the program was created or compiled. This resulting compatibility of the computer program is achieved because the invention protects the precedence of operations within the computer program using latency assumptions which were used when creating the computer program. When the computer program is created, latency assumption information is efficiently provided within the computer program. Thereafter, when the computer program is executed, it is able to advise the processing system of the latency assumptions with which it was created. Various ways are described in which the processing system can utilize the latency assumptions when executing the computer program so as to ensure compatibility.
摘要翻译：公开了一种方法和系统，其允许计算机程序在目标代码兼容的处理系统中正确地执行，该处理系统的延迟与程序被创建或编译的时间不同。实现计算机程序的这种兼容性是因为本发明使用在创建计算机程序时使用的延迟假设来保护计算机程序内的操作的优先级。当创建计算机程序时，计算机程序内有效地提供延迟假设信息。此后，当执行计算机程序时，能够向处理系统通知其创建的延迟假设。描述了各种方式，其中处理系统可以在执行计算机程序时利用延迟假设，以确保兼容性。

10. 发明授权

US6023751A Computer system and method for evaluating predicates and Boolean expressions 失效
标题翻译：用于评估谓词和布尔表达式的计算机系统和方法
公开(公告)号：US6023751A
公开(公告)日：2000-02-08
申请号：US400414
申请日：1995-03-03
申请人： Michael Schlansker , B. Ramakrishna Rau , Vinod Kathail
发明人： Michael Schlansker , B. Ramakrishna Rau , Vinod Kathail
IPC分类号： G06F9/38 , G06F7/00 , G06F7/60 , G06F9/305 , G06F9/32 , G06F15/00
CPC分类号： G06F9/30029 , G06F7/00
摘要： A computer system provides fast evaluation of predicates and Boolean expressions with a set of operations for determining a value in a specified register from a plurality of inputs. The execution of each operation is defined by two functions of the operation's inputs: a result function which yields a result value, and an enable function which determines whether the result value is written to the specified register. To evaluate a Boolean expression with the operations, the register is preset to a Boolean value, e.g. one for an AND reduction, zero for an OR reduction. The operations can then write a Boolean value, e.g. zero for an AND reduction, one for an OR reduction, to the register if each operation's enable function evaluates true. The register then stores the correct value of the expression. The expression's value can be used as predicates to conditionally execute operations in a program. Preferably, the operations are executed in parallel by plural functional units, and the register is capable of accepting multiple values written simultaneously, so long as they are identical.
摘要翻译：计算机系统通过一组用于从多个输入中确定指定寄存器中的值的操作来提供对谓词和布尔表达式的快速评估。每个操作的执行由操作输入的两个功能定义：产生结果值的结果函数和确定结果值是否写入指定寄存器的使能函数。要使用这些操作来评估一个布尔表达式，寄存器被预置为布尔值，例如。一个用于和减少，零减少OR。然后，操作可以写一个布尔值，例如如果每个操作的启用功能评估为真，则为零减少一个用于OR减少的零。寄存器然后存储表达式的正确值。表达式的值可以用作谓词来有条件地执行程序中的操作。优选地，这些操作由多个功能单元并行执行，并且寄存器能够接受同时写入的多个值，只要它们相同即可。

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