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    • 3. 发明授权
    • Predictive processing method in a semiconductor processing facility
    • 半导体处理设备中的预测处理方法
    • US06766285B1
    • 2004-07-20
    • US09570305
    • 2000-05-12
    • Sam H. Allen, Jr.Michael R. ConboyJason Grover
    • Sam H. Allen, Jr.Michael R. ConboyJason Grover
    • G06F945
    • G05B19/41865G05B2219/32194G05B2219/32343G05B2219/45031H01L21/67276Y02P90/20Y02P90/22Y02P90/26
    • Wafer processing cycle times are substantially reduced by predicting and correcting downstream processing location anomalies before a wafer lot is released to the next processing location on the processing line. In an example embodiment, a method of verifying downstream processing line readiness in a semiconductor processing facility having a material handling system includes presenting a wafer lot to a first application processing location. A signal is then sent to a second application processing location to verify readiness by simulating the second application processing on the wafer lot. The availability or operating status of the second processing location is then communicated to the material handling system, the material handling system communicating instructions to the first processing location on where to send the wafer lot after the processing simulation is complete. The readiness verification method is repeated until the wafer lot is completely processed.
    • 通过在将晶片批次释放到处理线上的下一个处理位置之前预测和校正下游处理位置异常,可以大大减少晶片处理周期时间。 在一个示例性实施例中,一种在具有材料处理系统的半导体处理设备中验证下游处理线准备的方法包括将晶片批次呈现给第一应用处理位置。 然后将信号发送到第二应用处理位置,以通过模拟晶片批次上的第二应用处理来验证准备状态。 然后将第二处理位置的可用性或操作状态传送到材料处理系统,材料处理系统在处理模拟完成之后向第一处理位置传送指令发送晶片批次的指令。 重复准备验证方法,直到晶片批次完全处理。