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    • 3. 发明申请
    • FOUNDATION FIELDBUS SIMULATION SYSTEM
    • 基金会现场总线仿真系统
    • US20090132060A1
    • 2009-05-21
    • US12276089
    • 2008-11-21
    • Winston Jenks
    • Winston Jenks
    • G05B19/02G06G7/66
    • G05B17/02G05B2219/31135G05B2219/32343G05B2219/32355Y02P90/26
    • A method and system for simulating the control of a process with a controller. The method creates a virtual process scheme having virtual devices connected on a virtual bus, such as a Fieldbus. The virtual scheme also includes process information. The process scheme is stored in a read/write medium and configured for communication access by a controller. The communication configuration uses an actual bus in bus protocol, such as a Fieldbus protocol. The actual bus couples with the virtual bus to replicate actual “real world” communication across the particular bus protocol. The DCS generates and transmits control communication, such as control commands based on data representing the virtual scheme. The virtual scheme data is dynamically updated with an associated Information Handling System to replicate an actual dynamic process. The seamless communication link coupled with the dynamic virtual scheme data simulates process control for the DCS.
    • 一种用于模拟控制器对过程的控制的方法和系统。 该方法创建虚拟处理方案,其中虚拟设备连接在诸如现场总线的虚拟总线上。 虚拟方案还包括进程信息。 该处理方案被存储在读/写介质中并且被配置用于由控制器进行通信访问。 通信配置使用总线协议中的实际总线,如现场总线协议。 实际总线与虚拟总线耦合,以跨特定总线协议复制实际的“现实世界”通信。 DCS根据表示虚拟方案的数据生成并发送诸如控制命令之类的控制通信。 使用关联的信息处理系统动态更新虚拟方案数据,以复制实际的动态过程。 与动态虚拟方案数据相结合的无缝通信链路模拟DCS的过程控制。
    • 5. 发明授权
    • Machine tool performance evaluation apparatus and performance evaluation system equipped with the same
    • 机床性能评估仪器和性能评估系统配备相同
    • US06810360B2
    • 2004-10-26
    • US10260408
    • 2002-10-01
    • Makoto FujishimaYoshiaki Akamatsu
    • Makoto FujishimaYoshiaki Akamatsu
    • G06F1900
    • G05B19/404G05B2219/31156G05B2219/32343G05B2219/32352G05B2219/35008G05B2219/35017G05B2219/49219Y02P90/18Y02P90/26Y02P90/265
    • The present invention relates to a performance evaluation system constructed to efficiently collect and accumulate analysis conditions for use in three dimensional model analysis. The performance evaluation system 50 is constructed by connecting a plurality of performance evaluation apparatuses 1 provided in each machine tool to a management apparatus 52 via a network 51. Each performance evaluation apparatus 1 comprises an analysis data storing section 12 in which model data and condition data are stored, a detecting device 4 which detects actual performance, an analyzing section 13 which analyzes the performance, an evaluation determining section 15 which evaluates the correctness of the analyzed performance data, and a data updating section 16 which changes and updates the model data and the condition data. The management apparatus 52 comprises an analysis data accumulating section 61 which accumulates the model data and condition data received from the performance evaluation apparatus 1.
    • 本发明涉及一种能够有效收集和累积用于三维模型分析的分析条件的性能评估系统。 性能评估系统50通过将各机器中提供的多个性能评估装置1经由网络51连接到管理装置52而构成。每个性能评估装置1包括分析数据存储部分12,其中模型数据和条件数据 存储检测实际性能的检测装置4,对性能进行分析的分析部13,评价分析性能数据的正确性的评价判定部15以及改变和更新模型数据的数据更新部16,以及 条件数据。 管理装置52包括分析数据累积部61,累积从演奏评价装置1接收的模型数据和条件数据。
    • 9. 发明授权
    • Predictive processing method in a semiconductor processing facility
    • 半导体处理设备中的预测处理方法
    • US06766285B1
    • 2004-07-20
    • US09570305
    • 2000-05-12
    • Sam H. Allen, Jr.Michael R. ConboyJason Grover
    • Sam H. Allen, Jr.Michael R. ConboyJason Grover
    • G06F945
    • G05B19/41865G05B2219/32194G05B2219/32343G05B2219/45031H01L21/67276Y02P90/20Y02P90/22Y02P90/26
    • Wafer processing cycle times are substantially reduced by predicting and correcting downstream processing location anomalies before a wafer lot is released to the next processing location on the processing line. In an example embodiment, a method of verifying downstream processing line readiness in a semiconductor processing facility having a material handling system includes presenting a wafer lot to a first application processing location. A signal is then sent to a second application processing location to verify readiness by simulating the second application processing on the wafer lot. The availability or operating status of the second processing location is then communicated to the material handling system, the material handling system communicating instructions to the first processing location on where to send the wafer lot after the processing simulation is complete. The readiness verification method is repeated until the wafer lot is completely processed.
    • 通过在将晶片批次释放到处理线上的下一个处理位置之前预测和校正下游处理位置异常,可以大大减少晶片处理周期时间。 在一个示例性实施例中,一种在具有材料处理系统的半导体处理设备中验证下游处理线准备的方法包括将晶片批次呈现给第一应用处理位置。 然后将信号发送到第二应用处理位置,以通过模拟晶片批次上的第二应用处理来验证准备状态。 然后将第二处理位置的可用性或操作状态传送到材料处理系统,材料处理系统在处理模拟完成之后向第一处理位置传送指令发送晶片批次的指令。 重复准备验证方法,直到晶片批次完全处理。