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1. 发明授权

US5671392A Memory device circuit and method for concurrently addressing columns of multiple banks of multi-bank memory array 失效
标题翻译：用于同时寻址多行存储器阵列多列的存储器件电路和方法
公开(公告)号：US5671392A
公开(公告)日：1997-09-23
申请号：US419909
申请日：1995-04-11
申请人： Michael Parris , H. Kent Stalnaker
发明人： Michael Parris , H. Kent Stalnaker
IPC分类号： G11C11/407 , G11C8/12 , G11C11/401 , G11C29/28 , G11C29/34 , G06F12/00
CPC分类号： G11C8/12 , G11C29/28
摘要： A circuit and method for a memory device, such as a synchronous dynamic random access memory (SDRAM) having at least two memory banks. Columns of at least two memory banks are concurrently addressable to permit data to be written to, or read from, the at least two memory banks concurrently. By writing data concurrently to more than one memory bank, testing of the memory of the memory device can be effectuated in a reduced period of time. Data can also be written or read from a single bank in a multi-bank RAM without requiring that a particular bank be specified during a read/write command.
摘要翻译：一种用于存储器件的电路和方法，例如具有至少两个存储体的同步动态随机存取存储器（SDRAM）。至少两个存储体的列同时可寻址以允许数据同时写入或读取至少两个存储体。通过将数据同时写入多个存储体，可以在减少的时间段内对存储器件的存储器进行测试。也可以在多存储体RAM中从单个存储体中写入或读取数据，而不需要在读取/写入命令期间指定特定的存储体。

2. 发明授权

US07199084B2 Concentrated suspensions 有权
标题翻译：浓缩悬浮液
公开(公告)号：US07199084B2
公开(公告)日：2007-04-03
申请号：US10103221
申请日：2002-03-21
申请人： Michael Parris , Geoff Robinson
发明人： Michael Parris , Geoff Robinson
IPC分类号： C09K8/18 , C09K8/20
CPC分类号： C09K8/82 , C09K8/58 , C09K8/62 , C09K8/64
摘要： Suspensions are provided of water-soluble materials in non-aqueous carrier fluids using suspension agents that include thixotropic agents and, optionally, organophilic clays. Methods of forming such suspensions are provided. Methods are also provided for using such suspensions to prepare aqueous solutions, in particular thickened aqueous solutions, in particular for use in oilfield treatments.
摘要翻译：使用包括触变剂和任选的亲有机粘土的悬浮剂在非水载体流体中提供水溶性材料的悬浮液。提供了形成这种悬浮液的方法。还提供了使用这种悬浮液来制备水溶液，特别是增稠的水溶液，特别是用于油田处理的方法。

3. 发明授权

US5763298A Bond pad option for integrated circuits 失效
标题翻译：用于集成电路的焊盘选项
公开(公告)号：US5763298A
公开(公告)日：1998-06-09
申请号：US868179
申请日：1997-06-03
申请人： Michael Parris , Michael V. Cordoba
发明人： Michael Parris , Michael V. Cordoba
IPC分类号： H01L21/60 , H01L23/485 , H01L23/50 , H01L27/118 , H01L2/208
CPC分类号： H01L24/06 , H01L23/50 , H01L24/03 , H01L27/11898 , H01L2224/05554 , H01L2224/05599 , H01L2224/48247 , H01L2224/85385 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/14
摘要： An integrated circuit having a first and second bond pads, a latch circuit, and a voltage lead. Different configurations of the internal circuitry of the integrated circuit are selected by applying the voltage lead either to the first or second bond pads. This result is achieved because the latch circuit, coupled between the first and second bond pads, is capable of inverting the voltage response seen at the first bond pad.
摘要翻译：具有第一和第二接合焊盘，锁存电路和电压引线的集成电路。通过将电压引线施加到第一或第二接合焊盘来选择集成电路的内部电路的不同配置。实现该结果是因为耦合在第一和第二接合焊盘之间的锁存电路能够反转在第一接合焊盘处看到的电压响应。

4. 发明申请

US20060190676A1 Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks 有权
公开(公告)号：US20060190676A1
公开(公告)日：2006-08-24
申请号：US11064354
申请日：2005-02-23
申请人： Douglas Butler , Oscar Jones , Michael Parris , Kim Hardee
发明人： Douglas Butler , Oscar Jones , Michael Parris , Kim Hardee
IPC分类号： G06F13/28
CPC分类号： G06F12/0804 , G11C11/406 , G11C11/40607 , G11C11/4076
摘要： A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time.

5. 发明申请

US20060022742A1 Powergating method and apparatus 有权
标题翻译：电源起动方法和装置
公开(公告)号：US20060022742A1
公开(公告)日：2006-02-02
申请号：US10900505
申请日：2004-07-28
申请人： Michael Parris , Kim Hardee
发明人： Michael Parris , Kim Hardee
IPC分类号： H03K17/687
CPC分类号： H03K19/0016
摘要： A powergating circuit includes a P-channel transistor with a source coupled to VCC, a gate for receiving a first boosted or non-boosted powergating control signal, and a drain forming the internal switched VCC power supply. An N-channel transistor has a source coupled to VSS, a gate for receiving a second boosted or non-boosted powergating control signal, and a drain forming the internal switched VSS power supply. The powergating circuit further includes a circuit for forcing the first and second internal power supply voltages to a mid-point reference voltage during the standby mode.
摘要翻译：电源门控电路包括具有耦合到VCC的源极的P沟道晶体管，用于接收第一升压或非升压功率门控控制信号的栅极和形成内部开关VCC电源的漏极。 N沟道晶体管具有耦合到VSS的源极，用于接收第二升压或非升压的功率门控控制信号的栅极以及形成内部开关VSS电源的漏极。电源门电路还包括用于在待机模式期间将第一和第二内部电源电压强制为中点参考电压的电路。

6. 发明授权

US06881709B2 Viscosity reduction of viscoelastic surfactant based fluids 有权
公开(公告)号：US06881709B2
公开(公告)日：2005-04-19
申请号：US09826127
申请日：2001-04-04
申请人： Erik B. Nelson , Bernhard Lungwitz , Keith Dismuke , Mathew Samuel , Golchi Salamat , Trevor Hughes , Jesse Lee , Philip Fletcher , Diankui Fu , Richard Hutchins , Michael Parris , Gary John Tustin
发明人： Erik B. Nelson , Bernhard Lungwitz , Keith Dismuke , Mathew Samuel , Golchi Salamat , Trevor Hughes , Jesse Lee , Philip Fletcher , Diankui Fu , Richard Hutchins , Michael Parris , Gary John Tustin
IPC分类号： C09K8/536 , C09K8/62 , C09K8/72 , C09K8/74 , C09K8/92 , E21B43/26 , C09K3/00
CPC分类号： C09K8/92 , C09K8/536 , C09K8/62 , C09K8/72 , C09K8/74 , C09K2208/26 , Y10S507/921 , Y10S507/922
摘要： Methods and compositions are disclosed for controlled addition of components that decrease the viscosity of the viscoelastic surfactant fluids or for controlled changes in the electrolyte concentration or composition of the viscoelastic surfactant fluids. One aspect of the invention relates to the use of internal breakers with a delayed activation. Another aspect of the invention relates to the use of precursors that release a breaking system such as alcohol by a process such as melting, slow dissolution, reaction with a compound present in the fluid or added to the fluid during or after the step of injecting, rupture of an encapsulating coating and de-adsorption of a breaking agent absorbed into solid particles. In another aspect of the invention, alcohols are included in a pad to reduce the low-shear viscosity and reduce the resistance to flow of the treatment fluids during a desired phase of the treatment.

7. 发明授权

US4893272A Ferroelectric retention method 失效
标题翻译：铁电保留法
公开(公告)号：US4893272A
公开(公告)日：1990-01-09
申请号：US184996
申请日：1988-04-22
申请人： S. Sheffield Eaton, Jr. , Douglas Butler , Michael Parris
发明人： S. Sheffield Eaton, Jr. , Douglas Butler , Michael Parris
IPC分类号： G11C11/41 , G11C11/22 , G11C14/00 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792
CPC分类号： G11C11/22
摘要： Polarization retention of a ferroelectric material in a memory cell is improved by open circuiting the write pulse. The depolarizing field is reduced by allowing charge to dissipate through the ferroelectric material, causing a polarizing field.

8. 发明申请

US20070114035A1 Method and composition of preparing polymeric fracturing fluids 有权
$Method and composition of preparing polymeric fracturing fluids$
标题翻译：制备聚合物压裂液的方法和组成
公开(公告)号：US20070114035A1
公开(公告)日：2007-05-24
申请号：US11285440
申请日：2005-11-22
申请人： Michael Parris , Ismail El Kholy
发明人： Michael Parris , Ismail El Kholy
IPC分类号： E21B43/267 , E21B43/26
CPC分类号： C09K8/68 , C09K8/685 , C09K8/88 , C09K8/887
摘要： In the presence of certain polyols, a guar gum or similar polysaccharide thickener solution is boron crosslinked before achievement of complete hydration of the thickener, without compromising the viscosity level achieved in a fracturing fluid by the time it is pumped into the wellbore and fractures the subterranean formation adjacent the wellbore. Methods continuously involve hydrating a polysaccharide thickener to an extent of 10% to 75%, but less than full hydration. Before 75% hydration is exceeded, a boron crosslinker is added. Upon addition of the boron crosslinker, the fluid is injected into the wellbore to stimulate hydrocarbon production. Because less time is needed for hydration, well site mixing equipment is down-sized smaller to achieve better efficiency and cost savings.
摘要翻译：在存在某些多元醇的情况下，瓜尔胶或类似的多糖增稠剂溶液在实现增稠剂的完全水合之前是交联的硼，而不损害在压裂液被泵入井筒中时达到的粘度水平，并破裂了地下形成在井眼附近。方法连续地将多糖增稠剂水合至10％至75％，但不足于完全水合。在超过75％水合之前，加入硼交联剂。加入硼交联剂后，将流体注入井眼以刺激烃的生产。由于水合时间较短，井场混合设备规模较小，可实现更好的效率和成本节约。

9. 发明申请

US20060005053A1 Cache and tag power-down function during low-power data retention standby mode technique for cached integrated circuit memory devices 审中-公开
标题翻译：用于缓存集成电路存储器件的低功耗数据保留待机模式技术中的缓存和标签掉电功能
公开(公告)号：US20060005053A1
公开(公告)日：2006-01-05
申请号：US10881767
申请日：2004-06-30
申请人： Oscar Jones , Douglas Butler , Michael Parris
发明人： Oscar Jones , Douglas Butler , Michael Parris
IPC分类号： G06F1/26
CPC分类号： G06F12/0804 , G06F1/3203 , G06F1/3275 , G06F2212/1028 , G06F2212/3042 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A cache and tag power-down function during low-power data retention standby mode technique for cached integrated circuit memory devices, in particular cached dynamic random access memory (DRAM) and cached static random access memory (SRAM), wherein the data in the cache is written back from cache to the main memory arrays (write-back operation) when power-down is entered such that the cache, tag and much of the cache control logic can be powered-down during power-down standby mode. If a DRAM cache is used, the refresh cycles can be inhibited to the DRAM cache, since it has been powered-down, so that additional power savings can be realized during self-refresh power-down standby. When power-down standby is exited, the cache operations are enabled as soon as the cache, tag and control circuitry are powered-up and a clear tag sequence is executed.
摘要翻译：用于缓存的集成电路存储器件（特别是缓存的动态随机存取存储器（DRAM））和高速缓存的静态随机存取存储器（SRAM）的低功率数据保持待机模式技术中的高速缓存和标签掉电功能，其中高速缓存中的数据在输入掉电时，从高速缓存写入主存储器阵列（回写操作），使得高速缓存，标签和大部分高速缓存控制逻辑在掉电待机模式下可以掉电。如果使用DRAM高速缓存，则可以禁止刷新周期到DRAM高速缓存，因为它已经掉电，从而在自刷新掉电待机期间可以实现额外的功率节省。当退出备用电源时，一旦高速缓存，标签和控制电路通电并且执行了清晰的标签序列，就启用高速缓存操作。

10. 发明授权

US4914627A One transistor memory cell with programmable capacitance divider 失效
标题翻译：一个具有可编程电容分压器的晶体管存储单元
公开(公告)号：US4914627A
公开(公告)日：1990-04-03
申请号：US292776
申请日：1989-01-03
申请人： S. Sheffield Eaton, Jr. , Michael Parris
发明人： S. Sheffield Eaton, Jr. , Michael Parris
IPC分类号： G11C11/22 , G11C14/00
CPC分类号： G11C14/0072 , G11C11/22 , G11C14/00
摘要： A transpolarizer is employed as a programmable capacitance divider. Two ferroelectric capacitors are coupled in series to form a common node and two extreme poles. The polarization of the two capacitors is set by grounding the two poles and then bringing them both up to VCC while impressing a voltage at the common node corresponding to data to be stored. Therefore, while one pole is held at VSS, the other pole is pulsed from VSS to VCC with the common node floating. A voltage develops at the common node which is above or below the midpoint between VSS and VCC, and will be indicative of the stored data. The capacitance divider is programmed in accordance with data. One such divider is added to a DRAM memory cell to form a shadow DRAM cell. Two such dividers are added to a static RAM memory cell to form a shadow static RAM cell. The same divider arrangement is operable in both volatile and non-volatile modes. An improvement arises by using PZT as dielectric in 54:46 mole ratio.
摘要翻译：偏振器用作可编程电容分压器。两个铁电电容器串联耦合以形成公共节点和两个极端极。两个电容器的极化通过将两极接地而设置，然后将它们两者都设置为VCC，同时在与要存储的数据相对应的公共节点处施加电压。因此，当一个极点保持在VSS时，另一个极点从VSS脉冲到VCC，公共节点浮动。在VSS和VCC之间的中点之上或之下的公共节点处产生电压，并且将指示存储的数据。电容分压器根据数据进行编程。一个这样的分频器被添加到DRAM存储器单元以形成阴影DRAM单元。将两个这样的分频器添加到静态RAM存储器单元中以形成阴影静态RAM单元。相同的分配器布置可在易失性和非易失性模式下操作。通过使用PZT作为54:46摩尔比的电介质来改善。

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