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    • 1. 发明授权
    • Flexible processing hardware architecture
    • 灵活的处理硬件架构
    • US07062578B2
    • 2006-06-13
    • US09977413
    • 2001-10-15
    • David C. DaviesMichael P. GreenbergMichael J. WiltJohn E. Agapakis
    • David C. DaviesMichael P. GreenbergMichael J. WiltJohn E. Agapakis
    • G06F13/00H04N7/14
    • G06F13/4027G06T1/60G06T5/20
    • A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices. The architecture provides a method of loading an embedded system CPU's local memory with operating system and diagnostic code without the use of ROM or FLASH memory. A system and method of reserving memory is also disclosed which utilizes a dummy or surrogate board with little of no functionality but which has a class code of a common device such as an Ethernet card. The primary system BIOS will read the class code and reserve memory based on the surrogate card. The driver of the non-standard card such as an embedded processor, can then use the memory space allocated to the surrogate card by the BIOS.
    • 灵活的可重新配置的处理系统架构允许实现在单个设备上实施的各种处理系统配置,其优选地是PCI总线附加扩展板,附加的子卡通过PCI连接并与其电连接 夹层式连接器,并插入个人计算机PCI扩展槽。 该架构使用PCI总线作为嵌入式处理器的本地CPU总线,这不仅允许系统配置的灵活性,而且允许从主机CPU隐藏PCI设备以允许正确的系统启动。 当辅助PCI总线主机总线桥接器无法响应而不影响主机CPU或其他辅助PCI总线外围设备时,架构还允许重新引导嵌入式处理CPU。 该架构提供了一种使用操作系统和诊断代码加载嵌入式系统CPU本地存储器的方法,而无需使用ROM或FLASH存储器。 还公开了一种保留存储器的系统和方法,其利用具有很少功能但具有诸如以太网卡的公共设备的类代码的虚拟或替代板。 主系统BIOS将读取类代码,并根据代理卡预留内存。 非标准卡的驱动程序(如嵌入式处理器)可以使用由BIOS分配给替代卡的存储空间。
    • 2. 发明授权
    • Flexible processing hardware architecture
    • 灵活的处理硬件架构
    • US06308234B1
    • 2001-10-23
    • US09030411
    • 1998-02-25
    • David C. DaviesMichael P. GreenbergMichael J. WiltJohn E. Agapakis
    • David C. DaviesMichael P. GreenbergMichael J. WiltJohn E. Agapakis
    • G06F1300
    • G06F13/4027G06T1/60G06T5/20
    • A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices. The architecture provides a method of loading an embedded system CPU's local memory with operating system and diagnostic code without the use of ROM or FLASH memory. A system and method of reserving memory is also disclosed which utilizes a dummy or surrogate board with little of no functionality but which has a class code of a common device such as an Ethernet card. The primary system BIOS will read the class code and reserve memory based on the surrogate card. The driver of the non-standard card such as an embedded processor, can then use the memory space allocated to the surrogate card by the BIOS.
    • 灵活的可重新配置的处理系统架构允许实现在单个设备上实施的各种处理系统配置,其优选地是PCI总线附加扩展板,附加的子卡通过PCI连接并与其电连接 夹层式连接器,并插入个人计算机PCI扩展槽。 该架构使用PCI总线作为嵌入式处理器的本地CPU总线,这不仅允许系统配置的灵活性,而且允许从主机CPU隐藏PCI设备以允许正确的系统启动。 当辅助PCI总线主机总线桥接器无法响应而不影响主机CPU或其他辅助PCI总线外围设备时,架构还允许重新引导嵌入式处理CPU。 该架构提供了一种使用操作系统和诊断代码加载嵌入式系统CPU本地存储器的方法,而无需使用ROM或FLASH存储器。 还公开了一种保留存储器的系统和方法,其利用具有很少功能但具有诸如以太网卡的公共设备的类代码的虚拟或替代板。 主系统BIOS将读取类代码,并根据代理卡预留内存。 非标准卡的驱动程序(如嵌入式处理器)可以使用由BIOS分配给替代卡的存储空间。
    • 3. 发明授权
    • Data resampler for data processing system for logically adjacent data
samples
    • 用于逻辑相邻数据样本的数据处理系统的数据重采样器
    • US5977994A
    • 1999-11-02
    • US25938
    • 1998-02-19
    • Michael P. GreenbergMichael J. Wilt
    • Michael P. GreenbergMichael J. Wilt
    • G06F13/40G06F15/00G06T1/20G06T1/60G06T3/40G06T5/20G06F13/00
    • G06T3/4007G06F13/4027G06T1/60G06T5/20
    • A data resampler for a data processing system for logically adjacent data samples is provided. The data resampler includes a memory subsystem for storing samples to be rendered, a digital differential analyzer (DDA) for generating an interpolation corner address for a sample to be rendered and which also generates a set of interpolation fractions. The resampler also includes a fetch unit, which receives the generated interpolation corner address and generates four source addresses of samples to be fetched from the memory subsystem. A number of memory units are included in the resampler. The first memory unit is a first in, first out FIFO memory, for holding the generated interpolation fractions and for permitting the DDA and fetch unit to continue to operate during memory read latency periods. The second memory unit is also a FIFO memory and is used to hold pixel data. The resampler further includes an interpolation unit, which receives pixel data from the second FIFO memory unit and interpolation fractions from the first FIFO memory unit. The interpolation unit then computes rendered result pixels, assembles the result pixels into memory words and outputs the words to a destination memory address, which is supplied by an address generator in a destination memory subsystem via a third FIFO memory unit.
    • 提供了一种用于逻辑相邻数据样本的数据处理系统的数据重新采样器。 数据重采样器包括用于存储要渲染的样本的存储器子系统,用于生成待渲染样本的插值角地址并且还生成一组插值分数的数字差分分析器(DDA)。 重采样器还包括获取单元,其接收所生成的插值角地址,并生成要从存储器子系统取出的样本的四个源地址。 重新采样器中包含许多存储单元。 第一存储器单元是先进先出的FIFO存储器,用于保持生成的插值分数,并允许DDA和获取单元在存储器读取等待时间期间继续操作。 第二存储器单元也是FIFO存储器,用于保存像素数据。 再采样器还包括内插单元,其接收来自第二FIFO存储器单元的像素数据和来自第一FIFO存储器单元的插值分数。 插值单元然后计算渲染结果像素,将结果像素组装成存储字,并将该字输出到目的地存储器地址,该目的地存储器地址由目的地存储器子系统中的地址发生器经由第三FIFO存储器单元提供。
    • 9. 发明申请
    • AIR TRAP FOR A MEDICAL INFUSION DEVICE
    • 用于医疗输液装置的气囊
    • US20090107335A1
    • 2009-04-30
    • US12199166
    • 2008-08-27
    • Michael J. WiltJason A. Demers
    • Michael J. WiltJason A. Demers
    • B01D19/00
    • A61M1/3627A61M1/14B01D19/00
    • An air trap for a blood circuit and method for removing air from blood in a dialysis unit. The air trap may include a blood inlet supply line, a blood outlet supply line, and a container having an approximately spherical internal wall, an inlet at a top end of the container connected to the blood inlet supply line, and an outlet at a bottom end of the container connected to the blood outlet supply line. The inlet may be offset from a vertical axis of the approximately spherical internal wall such that blood entering the container is directed to flow in a spiral-like path. The inlet port may be arranged to introduce blood into the container in a direction that is approximately tangential to the approximately spherical inner wall of the container and/or in a direction that is approximately perpendicular to the vertical axis of the container.
    • 用于血液回路的空气阱和用于从透析单元中的血液中除去空气的方法。 空气阱可以包括血液入口供应管线,血液出口供应管线和具有近似球形内壁的容器,容器顶端的入口连接到血液入口供应管线,以及底部出口 容器的端部连接到血液出口供应管线。 入口可以偏离近似球形的内壁的垂直轴线,使得进入容器的血液被引导成螺旋形路径流动。 入口端口可以布置成以与容器的近似球形内壁大致相切的方向和/或大致垂直于容器的垂直轴线的方向将血液引入容器。