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1. 发明授权

US5977994A Data resampler for data processing system for logically adjacent data samples 失效
标题翻译：用于逻辑相邻数据样本的数据处理系统的数据重采样器
公开(公告)号：US5977994A
公开(公告)日：1999-11-02
申请号：US25938
申请日：1998-02-19
申请人： Michael P. Greenberg , Michael J. Wilt
发明人： Michael P. Greenberg , Michael J. Wilt
IPC分类号： G06F13/40 , G06F15/00 , G06T1/20 , G06T1/60 , G06T3/40 , G06T5/20 , G06F13/00
CPC分类号： G06T3/4007 , G06F13/4027 , G06T1/60 , G06T5/20
摘要： A data resampler for a data processing system for logically adjacent data samples is provided. The data resampler includes a memory subsystem for storing samples to be rendered, a digital differential analyzer (DDA) for generating an interpolation corner address for a sample to be rendered and which also generates a set of interpolation fractions. The resampler also includes a fetch unit, which receives the generated interpolation corner address and generates four source addresses of samples to be fetched from the memory subsystem. A number of memory units are included in the resampler. The first memory unit is a first in, first out FIFO memory, for holding the generated interpolation fractions and for permitting the DDA and fetch unit to continue to operate during memory read latency periods. The second memory unit is also a FIFO memory and is used to hold pixel data. The resampler further includes an interpolation unit, which receives pixel data from the second FIFO memory unit and interpolation fractions from the first FIFO memory unit. The interpolation unit then computes rendered result pixels, assembles the result pixels into memory words and outputs the words to a destination memory address, which is supplied by an address generator in a destination memory subsystem via a third FIFO memory unit.
摘要翻译：提供了一种用于逻辑相邻数据样本的数据处理系统的数据重新采样器。数据重采样器包括用于存储要渲染的样本的存储器子系统，用于生成待渲染样本的插值角地址并且还生成一组插值分数的数字差分分析器（DDA）。重采样器还包括获取单元，其接收所生成的插值角地址，并生成要从存储器子系统取出的样本的四个源地址。重新采样器中包含许多存储单元。第一存储器单元是先进先出的FIFO存储器，用于保持生成的插值分数，并允许DDA和获取单元在存储器读取等待时间期间继续操作。第二存储器单元也是FIFO存储器，用于保存像素数据。再采样器还包括内插单元，其接收来自第二FIFO存储器单元的像素数据和来自第一FIFO存储器单元的插值分数。插值单元然后计算渲染结果像素，将结果像素组装成存储字，并将该字输出到目的地存储器地址，该目的地存储器地址由目的地存储器子系统中的地址发生器经由第三FIFO存储器单元提供。

2. 发明授权

US07062578B2 Flexible processing hardware architecture 有权
标题翻译：灵活的处理硬件架构
公开(公告)号：US07062578B2
公开(公告)日：2006-06-13
申请号：US09977413
申请日：2001-10-15
申请人： David C. Davies , Michael P. Greenberg , Michael J. Wilt , John E. Agapakis
发明人： David C. Davies , Michael P. Greenberg , Michael J. Wilt , John E. Agapakis
IPC分类号： G06F13/00 , H04N7/14
CPC分类号： G06F13/4027 , G06T1/60 , G06T5/20
摘要： A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices. The architecture provides a method of loading an embedded system CPU's local memory with operating system and diagnostic code without the use of ROM or FLASH memory. A system and method of reserving memory is also disclosed which utilizes a dummy or surrogate board with little of no functionality but which has a class code of a common device such as an Ethernet card. The primary system BIOS will read the class code and reserve memory based on the surrogate card. The driver of the non-standard card such as an embedded processor, can then use the memory space allocated to the surrogate card by the BIOS.
摘要翻译：灵活的可重新配置的处理系统架构允许实现在单个设备上实施的各种处理系统配置，其优选地是PCI总线附加扩展板，附加的子卡通过PCI连接并与其电连接夹层式连接器，并插入个人计算机PCI扩展槽。该架构使用PCI总线作为嵌入式处理器的本地CPU总线，这不仅允许系统配置的灵活性，而且允许从主机CPU隐藏PCI设备以允许正确的系统启动。当辅助PCI总线主机总线桥接器无法响应而不影响主机CPU或其他辅助PCI总线外围设备时，架构还允许重新引导嵌入式处理CPU。该架构提供了一种使用操作系统和诊断代码加载嵌入式系统CPU本地存储器的方法，而无需使用ROM或FLASH存储器。还公开了一种保留存储器的系统和方法，其利用具有很少功能但具有诸如以太网卡的公共设备的类代码的虚拟或替代板。主系统BIOS将读取类代码，并根据代理卡预留内存。非标准卡的驱动程序（如嵌入式处理器）可以使用由BIOS分配给替代卡的存储空间。

3. 发明授权

US06308234B1 Flexible processing hardware architecture 失效
标题翻译：灵活的处理硬件架构
公开(公告)号：US06308234B1
公开(公告)日：2001-10-23
申请号：US09030411
申请日：1998-02-25
申请人： David C. Davies , Michael P. Greenberg , Michael J. Wilt , John E. Agapakis
发明人： David C. Davies , Michael P. Greenberg , Michael J. Wilt , John E. Agapakis
IPC分类号： G06F1300
CPC分类号： G06F13/4027 , G06T1/60 , G06T5/20
摘要： A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices. The architecture provides a method of loading an embedded system CPU's local memory with operating system and diagnostic code without the use of ROM or FLASH memory. A system and method of reserving memory is also disclosed which utilizes a dummy or surrogate board with little of no functionality but which has a class code of a common device such as an Ethernet card. The primary system BIOS will read the class code and reserve memory based on the surrogate card. The driver of the non-standard card such as an embedded processor, can then use the memory space allocated to the surrogate card by the BIOS.
摘要翻译：灵活的可重新配置的处理系统架构允许实现在单个设备上实施的各种处理系统配置，其优选地是PCI总线附加扩展板，附加的子卡通过PCI连接并与其电连接夹层式连接器，并插入个人计算机PCI扩展槽。该架构使用PCI总线作为嵌入式处理器的本地CPU总线，这不仅允许系统配置的灵活性，而且允许从主机CPU隐藏PCI设备以允许正确的系统启动。当辅助PCI总线主机总线桥接器无法响应而不影响主机CPU或其他辅助PCI总线外围设备时，架构还允许重新引导嵌入式处理CPU。该架构提供了一种使用操作系统和诊断代码加载嵌入式系统CPU本地存储器的方法，而无需使用ROM或FLASH存储器。还公开了一种保留存储器的系统和方法，其利用具有很少功能但具有诸如以太网卡的公共设备的类代码的虚拟或替代板。主系统BIOS将读取类代码，并根据代理卡预留内存。非标准卡的驱动程序（如嵌入式处理器）可以使用由BIOS分配给替代卡的存储空间。

4. 发明授权

US3944984A Computer controller system with a reprogrammable read only memory 失效
标题翻译：计算机控制器系统具有可重新编程的只读存储器
公开(公告)号：US3944984A
公开(公告)日：1976-03-16
申请号：US463281
申请日：1974-04-23
申请人： Richard E. Morley , Michael P. Greenberg
发明人： Richard E. Morley , Michael P. Greenberg
IPC分类号： G05B15/02 , G05B19/02 , G05B19/05 , G06F9/06 , G06F9/24 , G06F15/46 , G06F9/16
CPC分类号： G06F9/24 , G05B19/056 , G05B2219/13013 , G05B2219/13128 , G05B2219/13142 , G05B2219/15048
摘要： A miniaturized computer controller system utilizes reprogrammable "read only" ultraviolet memory chips instead of conventional core memories to store a control program comprising variable information regarding all electrical elements in all electrical circuit lines of the controller. The memory chips are reprogrammable within the controller and thus delicate removal of the chips for reprogramming is eliminated. The controller utilizes a central processor removably interfitting with a reprogramming module that also communicates with a programming panel.When in a "monitor" mode, the programming panel, in conjunction with the reprogramming module, allows the operator to view any particular electrical circuit line while the controller is operating. A scroll switch on the programming panel further allows the operator to view sequentially higher or lower numbered electrical circuit lines while a trace switch provides for examining any electrical circuit line to which a currently viewed element is referenced.When in a " program" mode, the programming panel, in combination with the reprogramming module, replaces the variable memory "read only" chips and allows the controller to continue operation while the operator is programming, adjusting, or de-bugging the electrical circuit lines. Following the programming of the electrical circuit lines with the desired electrical elements, the information regarding these lines is transferred to the reprogrammable "read only" memory chips when the programming panel is in a "write" mode. In this mode all the information previously stored in the memory chips is first erased by ultraviolet light, followed by the insertion of the new information regarding the electrical circuit lines.Following the transferral of information to the memory chips, the reprogramming module is disconnected from the central processor and replaced by a removably interfitting power supply module, whereby the system operates with electrical circuit line information stored in the reprogrammable memory chips.
摘要翻译：微型计算机控制器系统利用可再编程的“只读”紫外线存储器芯片，而不是传统的核心存储器来存储包括关于控制器的所有电路线中的所有电气元件的可变信息的控制程序。存储器芯片在控制器内可重新编程，因此消除了用于重新编程的芯片的精细去除。控制器利用中央处理器与可编程面板进行通信的可重新编程模块进行可拆卸的配合。

5. 发明授权

US4581762A Vision inspection system 失效
标题翻译：视力检查系统
公开(公告)号：US4581762A
公开(公告)日：1986-04-08
申请号：US572570
申请日：1984-01-19
申请人： Stanley N. Lapidus , Joseph J. Dziezanowski , Seymour A. Friedel , Michael P. Greenberg
发明人： Stanley N. Lapidus , Joseph J. Dziezanowski , Seymour A. Friedel , Michael P. Greenberg
IPC分类号： G06T7/00 , G06K9/46
CPC分类号： G06T7/001 , G06T2207/30164
摘要： A vision inspection system operable with foreground illumination provides user identification of selected regions of a known object for later comparison to an unknown object. A gray scale pixel array of each selected region is processed for edges and this processed data array is stored as a template for each region. Gray scale illumination data from larger corresponding areas of the unknown object are processed for edges to form gradient maps. The first template is iteratively compared to the first gradient map. A correlation value greater than a threshold value causes the system to examine the second and possibly third gradient maps on the unknown object. Distance and angular relationships of the regions are used to both identify and orient the object under test. Once the unknown object is identified and its orientation determined, various visual attributes and measurements of the object can be determined through use of visual tools.
摘要翻译：可用前景照明操作的视觉检查系统提供用户识别已知对象的选定区域，以便稍后与未知对象进行比较。对于边缘处理每个所选区域的灰度像素阵列，并且将该处理的数据阵列存储为每个区域的模板。针对未知对象的较大对应区域的灰度照明数据进行边缘处理，形成梯度图。将第一个模板与第一个梯度图进行迭代比较。大于阈值的相关值导致系统检查未知对象上的第二和第三梯度图。区域的距离和角度关系用于识别和定向被测物体。一旦识别出未知对象并确定其方向，就可以通过使用可视化工具确定对象的各种视觉属性和测量。

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