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1. 发明申请

US20080034193A1 System and Method for Providing a Mediated External Exception Extension for a Microprocessor 审中-公开
标题翻译：为微处理器提供介入的外部异常扩展的系统和方法
公开(公告)号：US20080034193A1
公开(公告)日：2008-02-07
申请号：US11462601
申请日：2006-08-04
申请人： Michael N. Day , Jonathan J. DeMent , Charles R. Johns , Orran Y. Krieger , Cathy May
发明人： Michael N. Day , Jonathan J. DeMent , Charles R. Johns , Orran Y. Krieger , Cathy May
IPC分类号： G06F7/38
CPC分类号： G06F13/24 , G06F9/32 , G06F9/4812 , G06F2209/481
摘要： A system and method for providing a mediated external exception extension for a microprocessor are provided. With the system and method, in response to an external exception, a hypervisor determines if the associated external interrupt is directed to a logical partition (LPAR) that has external interrupt handling enabled. If so, the hypervisor sets appropriate state restore registers (SRRs) and passes control to an external interrupt handler of the LPAR. If external interrupt handling is not currently enabled by the LPAR, the hypervisor sets a mediated exception request and returns control to the LPAR. Once the operating system of the logical partition re-enables external interrupt handling, a mediated external interrupt occurs, state information for the LPAR is set in the SRRs, and the external interrupt handler of the LPAR is invoked. In this way, external interrupts may be received by the hypervisor even when external interrupt handling is disabled.
摘要翻译：提供了一种用于为微处理器提供介导的外部异常扩展的系统和方法。利用系统和方法，响应于外部异常，管理程序确定相关联的外部中断是否被引导到启用了外部中断处理的逻辑分区（LPAR）。如果是这样，管理程序设置适当的状态恢复寄存器（SRR），并将控制权传递给LPAR的外部中断处理程序。如果LPAR当前未启用外部中断处理，管理程序将设置介入的异常请求并将控制权返回给LPAR。一旦逻辑分区的操作系统重新启用外部中断处理，就会发生中介的外部中断，LPAR的状态信息设置在SRR中，并且调用LPAR的外部中断处理程序。以这种方式，即使禁用外部中断处理，管理程序也可以接收外部中断。

2. 发明授权

US08010763B2 Hypervisor-enforced isolation of entities within a single logical partition's virtual address space 有权
标题翻译：管理程序强制隔离单个逻辑分区的虚拟地址空间内的实体
公开(公告)号：US08010763B2
公开(公告)日：2011-08-30
申请号：US12111041
申请日：2008-04-28
申请人： William J. Armstrong , Orran Y. Krieger , Cathy May , Michal Ostrowski , Randal C. Swanberg
发明人： William J. Armstrong , Orran Y. Krieger , Cathy May , Michal Ostrowski , Randal C. Swanberg
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/455
CPC分类号： G06F12/1475 , G06F9/45558 , G06F12/1491 , G06F2009/45583 , G06F2009/45587 , G06F2212/1056
摘要： Access control to shared virtual address space within a single logical partition is provided. The access control includes: associating, by a hypervisor of the data processing system, a memory protection key with a portion of a single logical partition's virtual address space being shared by multiple entities, the key preventing access by one of the multiple entities to that portion of the virtual address space, and allowing access by another of the entities to that portion of the virtual address space; and locking by the hypervisor the memory protection key from modification by the one entity, wherein the locking prevents the one entity from modifying the key and thereby gaining access to the portion of the single logical partition's virtual address space with the associated memory protection key. In one embodiment, the one entity is the single logical partition itself, and the another entity is a partition adjunct.
摘要翻译：提供对单个逻辑分区内的共享虚拟地址空间的访问控制。访问控制包括：通过数据处理系统的管理程序将存储器保护密钥与多个实体共享的单个逻辑分区的虚拟地址空间的一部分相关联，该密钥阻止多个实体之一对该部分的访问的虚拟地址空间，并允许另一个实体访问该虚拟地址空间的该部分; 以及由所述管理程序锁定所述存储器保护密钥以免由所述一个实体修改，其中所述锁定防止所述一个实体修改所述密钥，从而利用所述相关联的存储器保护密钥访问所述单个逻辑分区的虚拟地址空间的所述部分。在一个实施例中，一个实体是单个逻辑分区本身，另一实体是分区附件。

3. 发明授权

US09244846B2 Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses 有权
标题翻译：确保交易存储访问的因果关系与非事务性存储访问进行交互
公开(公告)号：US09244846B2
公开(公告)日：2016-01-26
申请号：US13543325
申请日：2012-07-06
申请人： Bradly G. Frey , Cathy May , Derek E. Williams
发明人： Bradly G. Frey , Cathy May , Derek E. Williams
IPC分类号： G06F12/08 , G06F9/46
CPC分类号： G06F12/0842 , G06F9/466 , G06F12/0813 , G06F12/0831
摘要： A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional memory instructions include a non-transactional store instruction. The data processing system commits the memory transaction to the distributed shared memory system only in response to enforcement of causality of the non-transactional store instruction with respect to the memory transaction.
摘要翻译：数据处理系统为分布式共享存储器系统实现弱一致性存储器模型。数据处理系统在多个处理器核心上同时执行存储器事务内的一个或多个事务存储器指令和一个或多个非事务存储器指令。一个或多个非事务存储器指令包括非事务存储指令。数据处理系统只是为了响应于关于存储器事务的非事务性存储指令的因果关系的强制而将存储器事务提交给分布式共享存储器系统。

4. 发明申请

US20140013055A1 ENSURING CAUSALITY OF TRANSACTIONAL STORAGE ACCESSES INTERACTING WITH NON-TRANSACTIONAL STORAGE ACCESSES 审中-公开
标题翻译：确保与非交易存储访问交互的交易存储访问的原理
公开(公告)号：US20140013055A1
公开(公告)日：2014-01-09
申请号：US13777161
申请日：2013-02-26
申请人： Bradly G. Frey , Cathy May , Derek E. Williams
发明人： Bradly G. Frey , Cathy May , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F9/466 , G06F12/0813 , G06F12/0831
摘要： A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional memory instructions include a non-transactional store instruction. The data processing system commits the memory transaction to the distributed shared memory system only in response to enforcement of causality of the non-transactional store instruction with respect to the memory transaction.
摘要翻译：数据处理系统为分布式共享存储器系统实现弱一致性存储器模型。数据处理系统在多个处理器核心上同时执行存储器事务内的一个或多个事务存储器指令和一个或多个非事务存储器指令。一个或多个非事务存储器指令包括非事务存储指令。数据处理系统只是为了响应于关于存储器事务的非事务性存储指令的因果关系的强制而将存储器事务提交给分布式共享存储器系统。

5. 发明申请

US20120246658A1 Transactional Memory Preemption Mechanism 失效
公开(公告)号：US20120246658A1
公开(公告)日：2012-09-27
申请号：US13465115
申请日：2012-05-07
申请人： Richard L. Arndt , Harold W. Cain, III , Bradly G. Frey , Cathy May
发明人： Richard L. Arndt , Harold W. Cain, III , Bradly G. Frey , Cathy May
IPC分类号： G06F9/46
CPC分类号： G06F9/466 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/3863
摘要： Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.

6. 发明申请

US20120084477A1 Transactional Memory Preemption Mechanism 失效
标题翻译：事务记忆抢占机制
公开(公告)号：US20120084477A1
公开(公告)日：2012-04-05
申请号：US12894308
申请日：2010-09-30
申请人： Richard L. Arndt , Harold W. Cain, III , Bradly G. Frey , Cathy May
发明人： Richard L. Arndt , Harold W. Cain, III , Bradly G. Frey , Cathy May
IPC分类号： G06F13/24
CPC分类号： G06F9/466 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/3863
摘要： Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.
摘要翻译：提供了在数据处理系统中执行事务的机制。在处理器的内部寄存器中生成事务检查点数据结构。事务检查点数据结构存储表示执行相应事务之前的时间的程序寄存器的状态的事务检查点数据。执行包括由处理器执行的代码的第一部分的事务。在执行事务时接收事务的中断，结果，事务检查点数据被存储到数据处理系统的存储器中的数据结构。然后执行第二部分代码。响应于发生的事件导致处理器的执行切换返回到事务的执行，使用数据处理系统的存储器中的数据结构恢复程序寄存器的状态。

7. 发明申请

US20100268885A1 SPECIFYING AN ACCESS HINT FOR PREFETCHING LIMITED USE DATA IN A CACHE HIERARCHY 失效
标题翻译：指定访问提示用于缓存缓存中的有限使用数据
公开(公告)号：US20100268885A1
公开(公告)日：2010-10-21
申请号：US12424681
申请日：2009-04-16
申请人： Bradly G. Frey , Guy L. Guthrie , Cathy May , Balaram Sinharoy , Peter K. Szwed
发明人： Bradly G. Frey , Guy L. Guthrie , Cathy May , Balaram Sinharoy , Peter K. Szwed
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0897 , G06F2212/6028
摘要： A system and method for specifying an access hint for prefetching limited use data. A processing unit receives a data cache block touch (DCBT) instruction having an access hint indicating to the processing unit that a program executing on the data processing system may soon access a cache block addressed within the DCBT instruction. The access hint is contained in a code point stored in a subfield of the DCBT instruction. In response to detecting that the code point is set to a specific value, the data addressed in the DCBT instruction is prefetched into an entry in the lower level cache. The entry may then be updated as a least recently used entry of a plurality of entries in the lower level cache. In response to a new cache block being fetched to the cache, the prefetched cache block is cast out of the cache.
摘要翻译：一种用于指定预取有限使用数据的访问提示的系统和方法。处理单元接收具有指示给处理单元的访问提示的数据高速缓存块触摸（DCBT）指令，即在数据处理系统上执行的程序可以很快访问在DCBT指令内寻址的高速缓存块。访问提示包含在存储在DCBT指令的子字段中的代码点中。响应于检测到代码点被设置为特定值，DCBT指令中寻址的数据被预取到低级缓存中的条目中。然后可以将条目作为较低级别高速缓存中的多个条目的最近最少使用的条目来更新。响应于将新的高速缓存块提取到高速缓存，预取的高速缓存块被抛出高速缓存。

8. 发明授权

US08615644B2 Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition 有权
标题翻译：具有硬件线程控制逻辑的处理器，指示访问共享资源的指令在安全共享资源状态完成时指示禁用状态
公开(公告)号：US08615644B2
公开(公告)日：2013-12-24
申请号：US12708791
申请日：2010-02-19
申请人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
发明人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
IPC分类号： G06F9/38
CPC分类号： G06F9/30101 , G06F9/30123 , G06F9/3851 , G06F9/3857
摘要： A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled.
摘要翻译：用于指示关于被禁用线程的安全共享资源状况的技术提供了一种用于向其他硬件线程提供快速指示的机制，临时禁用的线程不再影响共享资源，例如共享专用寄存器和翻译查找，处理器核心内的缓冲区。来自核心内的流水线的信号表示流水线中的任何待执行的任何指示是否影响共享资源，如果没有，则通过线程状态寄存器中的状态更改将线程禁用状态呈现给其他线程。在接收到特定硬件线程被禁用的指示时，控制逻辑停止对特定硬件线程的指令的分派，然后等待直到由指令影响共享资源的任何指示已经被清除。然后控制逻辑更新线程状态以指示线程被禁用。

9. 发明授权

US08424015B2 Transactional memory preemption mechanism 失效
公开(公告)号：US08424015B2
公开(公告)日：2013-04-16
申请号：US12894308
申请日：2010-09-30
申请人： Richard L. Arndt , Harold W. Cain, III , Bradly G. Frey , Cathy May
发明人： Richard L. Arndt , Harold W. Cain, III , Bradly G. Frey , Cathy May
IPC分类号： G06F9/46 , G06F15/00 , G06F11/00 , G06F13/24
CPC分类号： G06F9/466 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/3863
摘要： Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.

10. 发明授权

US08140759B2 Specifying an access hint for prefetching partial cache block data in a cache hierarchy 失效
标题翻译：指定用于在缓存层次结构中预取部分高速缓存块数据的访问提示
公开(公告)号：US08140759B2
公开(公告)日：2012-03-20
申请号：US12424716
申请日：2009-04-16
申请人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
发明人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/0811 , G06F12/0817 , G06F2212/6028
摘要： A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.
摘要翻译：用于指定用于仅预取高速缓存块数据的子部分的访问提示的系统和方法，用于处理器核心的更有效的系统互连使用。处理单元接收包含访问提示的数据高速缓存块触摸（DCBT）指令，并且识别要预取的数据的特定大小部分。访问提示和对应于要预取的数据量的值都包含在DCBT指令的单独子字段中。响应于检测到代码点被设置为特定值，仅在DCBT指令的DCBT的子字段中标识的数据的特定大小被预取到低级缓存中的条目中。

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